Chapter 3 Gate-Level Minimization 3.35* Find the syntax errors in the following declarations (note that names for primitive gates are optional): module Exmpl-3(A, B, C, D, F) inputs output and I/ Line 1 A, B, C, Output D, F, // Line 2 // Line 3 // Line 4 I/ Line 5 I/ Line 6 I/ Line 7 B g1(A, B, D); (D, A, C), (F, B; C); not OR endmodule;

Answer parts A,B,C PLEASE! Please stop crediting the question back saying its incomplete, because I know its complete.

How would I complete the truth tables for these logic gates?  How do I know whether the transistor is closed (c) or open (o) for each '1' or '0' as listed for F outputs?

Which of the following package of IEEE contains most of the data conversion functions? std_logic_1164 std_logic std_logic_arith