Assuming a 5 stage pipeline that runs AVR assembly language, determine the average latency and throughput for the following assembly language commands for a pipeline that uses stalls only and a pipeline that combines stalls and forwarding. Express your answers using two decimal places. or r31, r9 ld r26, z st X, r15 sub r25, r26 ld r19, x QID0301 Stall Only Latency Stall Only Throughput Stall/Fwd Latency Stall/Fwd Throughput

Suppose we had a processor design with 5 stages where each stage takes the following amount of time: IF: 400 ps ID: 200 ps EX: 300 ps MEM: 500 ps WB: 200 psQ1: If you choose a pipelined design, what is the CPI? Assume that we have enough instructions such that the brief ramp up period at the beginning and the ramp down period at the end with less than 100% utilization does not matter. Q2: If you choose a pipelined design, what is the average execution time per instruction in picoseconds?

Write a code segment in MARIE assembly language to do the following: If X<Y, then X=16*X; Else Y=16*X+Y. To call a subroutine which will do TEMP=16*X, and try to minimize the number of instructions when you write the subroutine.

Consider the assembly code fragment related with the MSP430 given as below. The register contents and the values which are stored in a memory space before the code sequence is executed are given in the following table. The given code sequence fulfils some operations on these registers and the memory space. Considering all these issues, write down the register contents and the values stored in the memory space after executing the given code fragment. mexxx addib push addux push текл addux addib pop Registers Register Before The Program Executed After The Program Executed Memory Address Before The Program Executed After The Program Executed #0x1004, SP R5, R6 R6 @R7+, R5 R5 @R7, R8 (R8), 2(R8) R8, 0(R8) R8 R5 R6 R7 0x2515 0x1525 0x1004 0x1008 R8 SP 0x0000 0x1000 0x1002 0x1004 0x1006 0x1008 0x0001 0x1000 0x100E 0x1004 0X200E