Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN: 9780133594140
Author: James Kurose, Keith Ross
Publisher: PEARSON
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- In the memory architecture, the order of memory capacity from maximum to minimum is ( ).A, register - main memory - cache - auxiliary memory B, register - main memory - auxiliary storage - cacheC, auxiliary storage - main memory - cache - register D, register - cache - main memory - auxiliary storagearrow_forwardIf RAM (Random Access Memory) is a volatile memory, why do we need cache memory, which is transistor-based? Can computer memory be used for everything?arrow_forwardPlease answer all the following questions. 1. In a hypothetical computer, the processor has four registers: an 8-bit Program Counter (PC), a 16-bit Accumulator (AC), a 16-bit Counter (CTR), and a 12-bit Pointer (PTR). The memory is divided into words each of which is 16-bit long. Each word can hold either an instruction or a piece of data. For each instruction X, the four most significant bits (denoted by X15-12) represent an opcode. The rest of the instruction (denoted by X11-0) can be either an address or a value of an operand. The table below explains some of the instructions supported by the processor. Opcode (binary) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Operation Load AC from a memory location whose address is X11-0. Store AC into a memory location whose address is X11-0. Add to AC the contents of a memory location whose address is the value of PTR. The result is saved to AC. 1100 Subtract from AC the contents of a memory location whose address is the value…arrow_forward
- We have a memory that contains 10,988 bytes of data, so how much is the amount of data in that memory in kilobytes?arrow_forwardIn this section, please detail the amount of memory that can be addressed by the 20-bit address bus.arrow_forwardExtend the memory system of Fig. 12-4 to 4096 bytes of RAM and 4096 bytes of ROM. List the memory-address map and indicate what size decoders are needed. CPU A 16-11 10 7-1 RD W Da Decoder 8185 ADT RAM 889 AD ADT #5 Da Dut RAM2 ADT RAM3 RAM4 889 D ROM ADS Figure 12-4 Memory connection to the CPU.arrow_forward
- A memory has 8 megabytes of cells(a) What is the size of its MAR?(b) If 2-dimensional addressing is used, what is the size of each of the horizontaland vertical decoders?arrow_forwardGiven that RAM (Random Access Memory) is a storage medium that is subject to degradation over time, is it even possible for it to fulfill all of our requirements?arrow_forwardSuppose we have a 16KB byte-addressable memory that is 16-way low-order interleaved. What is the size of the memory address module offset field? Explain why.arrow_forward
- Design a 512 MByte memory using 64M*4 chips, with 8-bit read/write operations and byte addressability.arrow_forwardThere are two registers associated with memory (MAR and MDR), but why? b) What are the corresponding operations in the Little Man Computer?arrow_forwardSuppose computer has 4 Processor options, three hard disks , and four RAM. How many total combinations are there?arrow_forward
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