Assume (ABCD) sequence for 8421 code and (WXYZ) for 5211 code, what is the logic equation for Y obtained for 8421 to 5211 code conversion
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Step by step
Solved in 4 steps
- a) Create a 4 Variable Karnaugh Map in paper by mapping 1’s for given standard SOP Boolean expression. After mapping , make relevant groups within Karnaugh Map by considering rules for making groups for 4 variable Karnaugh Map. After making relevant grouping , extract the minimum SOP expression by considering rules for extracting minimum SOP using Karnaugh Map. * Standard SOP: *Create Circuit Diagram using logic gates and logic converter in Multisim for given standard SOP and minimum SOP which you have solved. Do make sure that truth table for both expressions should evaluate same result.Q2: For BCD code perform the following, with and without complement: 1. 1000010110 is subtracted from 10101000001. 2. 759 be subtracted from 645.2. Design a combinational logic circuit for 4-input majority circuit. A majority circuit is one which produces a HIGH (1) output when three or more inputs are HIGH (1). i. Construct the truth table and simplify the Boolean expression into SOP and POS forms using К-mаp. ii. Construct the logic diagram using AND-OR gate network with simplified SOP expression. iii. Construct the logic diagram using OR-AND gate network with simplified POS expression. iv. Construct the logic diagram using only NAND gates with simplified SOP expression. v. Construct the logic diagram using only NOR gates with simplified POS expression.
- Consider two binary numbers where the first is made of three bits whichcan be represented by X, Y, and Z, while the second is two bits and isrepresented by A and B. Design a logic circuit that multiplies X Y Z timesA B, using two half adders, one full adder in addition to AND gates.1-Using the Karnaugh Method, design and draw the circuit of the logic circuit that gives the result of the multiplication of the two-bit numbers "AB" and "CD" according to minterms (SOP). Do not make any further simplifications before or after the Karnaugh Method. In tables and Karnaugh, ensure that the least significant bit is on the far right and the entries are sorted alphabetically. Make sure that the circuit you have drawn is understandable, the function you have written and the truth table are readable.Write the vhdl code for 4-bit parallel-in parallel-out register using d flip flop
- 19: Select a suitable example for for combinational logic circuit. a. De-multiplexer b. Latches c. PLA d. None of the given choices 20: Random Access memory and Read Only Memory are semiconductor material Select one: True False 21: Decoder is a digital circuit which comprises both logic gates and memory elements. Select one: True False 23: Karnaugh Map can be drawn directly from maxterm (product-of-sums) Boolean expressions. Select one: True FalseLogic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions. Task 2: 4 INPUT PRIORITY ENCODERa) Write the truth table.b) Find the outputs in terms of min terms using minimal expression.c) By using K map, find the simple/simplest expression of theoutputs.d) Draw the circuit diagram. (Simulation design will be accepted.)e) Simulate the circuit & explain your results. (Please do notdesign separate simulations for each output. You should design ONEsimulation including all inputs and outputs.)A series of catchers that capture with serial information coming in the form of '1011' ; A) Design using T flip-flops ? B) Design using the register ?
- 6. F in the blanks in the truth table of the given digital circuit NOT Use fer NOT gate egX. Use paranthesis only for combining two logic gates OR and AND e ZOX+Y) er (Y+Z).OX+Y) You can use either XY or X.Y for AND gate. Write the letters in alphabetic orders: eg XY, not YX 1 5THE OUTPUT OF A LOGIC GATE IS 1 WHEN ALL ITS INPUTS ARE AT LOGIC 0. THE GATE IS EITHER а. an AND or an X-OR b. a NAND or an X-OR an OR or an X-NOR d. a NOR or an X-NORI was able to fill out the truth table for part A. I ONLY need help for PART B. B) Implement the logic function (z) using the multiplexer 74HC151 shows in the picture.