Implement a Logic Gate Design for this logic using Hex Inverter, 2-input nand, 4-input nand, and a D-Flip Flop
Implement a Logic Gate Design for this logic using Hex Inverter, 2-input nand, 4-input nand, and a D-Flip Flop
Power System Analysis and Design (MindTap Course List)
6th Edition
ISBN:9781305632134
Author:J. Duncan Glover, Thomas Overbye, Mulukutla S. Sarma
Publisher:J. Duncan Glover, Thomas Overbye, Mulukutla S. Sarma
Chapter3: Power Transformers
Section: Chapter Questions
Problem 3.30P: Reconsider Problem 3.29. If Va,VbandVc are a negative-sequence set, how would the voltage and...
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Implement a Logic Gate Design for this logic using Hex Inverter, 2-input nand, 4-input nand, and a D-Flip Flop. I have already provided k-maps, truth tables, and the flip flop that should be used for the gate design. Thank you for your help!
Transcribed Image Text:2 ST_IDLE
ST_GO
ST_STOP
Į
D
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
State Name
9
0
1
Q1
ܘ ܘ ܝ
QO
0 - Idle State, Yellow Light ON
1- The State with the Green Light ON
0 - The State with the Red Light ON
Q1+
Q1Q0
Y
Q1
Current State
ST_IDLE
ST_IDLE
ST_IDLE
ST_IDLE
ST_GO
ST_GO
ST_GO
ST_GO
ST_STOP
ST_STOP
ST_STOP
ST_STOP
unused
unused
unused
unused
▼
STOP, GO
▼
▼
00
01
11
10
QO
1
0011
၁ဝဝဝ
80000-0000
Q1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
00
0
0
X
1
Y = /Q0*/Q1
0
1
0
QO
✓
1
1
1
1
0
1
1
1
1
01
0
0
Q1+ = STOP * GO + Q1 */GO+/Q0 * STOP
X
0
1
0
0
STOP
✓
0
0
1
1
0
0
1
1
0
0
1
1
11
1
1
X
1
GO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
10
1
0
X
1
G
Q1
Next State
ST_IDLE
ST_GO
ST_STOP
ST_STOP
ST_IDLE
ST_GO
ST_IDLE
ST_STOP
ST_STOP
ST_GO
ST_STOP
ST_STOP
X
X
X
X
8
QO
0
1
Q1+
0
0
1
1
0
0
0
1
1
0
1
1
X
X
X
X
QO+
Q1Q0
G = Q0*/Q1
OOO
0
0
0
✓
QO+
0
1
0
0
0
1
0
0
0
1
0
0
X
X
X
X
STOP, GO
00
01
11
10
1
0
G
0
1
0
0
0
1
0
0
0
1
0
0
X
X
X
X
00
0
0
X
0
Y
1
0
0
0
1
0
1
0
0
0
0
0
X
X
X
X
Q0+ = /STOP * GO
01
1
1
X
1
R
Q1
R0011000
1
1
0
1
1
X
X
X
X
11
0
0
X
0
8
Q0
0
1
10
0
0
X
0
R = /Q0* Q1
0
01
1
-OO
0
0
Transcribed Image Text:TEXAS
INSTRUMENTS
www.ti.com
4 Pin Configuration and Functions
1CLR 11 14 Vcc
1D 2
13 2CLR
1CLK 3
12 2D
11:
1PRE 4
112CLK
1Q15 10 2PRE
1Q16
92Q
GND 7
820
FLIP-Flop
J, W, D, DB, N, NS, or PW package
14-Pin CDIP, CFP, SOIC, SSOP, PDIP, SO, or TSSOP
Top View
SN54HCT74, SN74HCT74
SCLS169F - DECEMBER 1982 - REVISED FEBRUARY 2022
1CLK 4
5
NC
1PRE
6
7
NC
1Q8
3 21 20 19
1Q
GND
NC
9 10 11 12 13
2QN
NC - No internal connection
18
2D
17
NC
16
2CLK
15
NC
14 2PRE
FK Package
20-Pin LCCC
Top View
+
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