Assume a program requires the execution of 75 ×106 FP instructions, 112 ×106 INT instructions, 88 ×106 L/S instructions, and 12 × 106 branch instructions. The CPI for each type of instruction is 1, 3, 4, and 2, respectively. Assume that the processor has a 2 GHz clock rate. a) By how much must we improve the CPI of FP instructions if we want the program to run two times faster? b) By how much must we improve the CPI of L/S instructions if we want the program to run two times faster? c) By how much is the execution time of the program improved if the CPI of INT and FP instructions is reduced by 40% and the CPI of L/S and Branch is reduced by 30%

H.W.: Consider a hypothetical machine with two steps instruction cycle: fetch cycle and execute cycle. The characteristics of the machine is given in Figure 8 with the following explanation: The processor contains a single data register, called an accumulator (AC). • Both instructions and data are 8 bits long. • The memory is organized using 8-bit words. • The instruction format provides 2 bits for the opcode, and up to 26 = 64 words of memory can be directly addressed. Opcode Address (a) Instruction format Magnitude (b) Integer format Program counter (PC)= Address of instruction Instruction register (IR)- Instruction being executed Accumulator (AC) Temporary storage (c) Internal CPU registers -Load AC from memory Store AC to memory - Add to AC from memory (d) Partial list of opcodes Figure 8 Characteristics of a Hypothetical Machine Figure 9 illustrates a partial program execution, showing the relevant portions of memory and processor registers after the first instruction, 64H has…

A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address, similar to Marie). Each instruction is stored in one word of memory. a) How many bits are needed for the opcode? b) How many bits are left for the address part of the instruction? c) What is the maximum allowable size for memory?

A certain microprocessor requires either 2, 4, 8, 12, or 16 machine cycles to perform various operations. A total of 17.5% of its instructions require 2 machine cycles, 12.5% require 4 machine cycles, 35% require 8 machine cycles, 20% require 12 machine cycles, and 15% require 16 machine cycles.Q) What is the clock rate (machine cycles per second) required for this microprocessor to be a “1 MIPS” processor?

Assume a 5-stage pipelined CPU (IF – ID – MU- EX – WR) requires following time for different sections: Required time 15 ns Pipeline stages Fetch Unit Decode Unit 10 ns 20 ns Memory Unit Execution Unit 8 ns 15 ns Write back Unit The maximum delay required to transfer contents from one state to another is 2ns. a) Show the time steps of pipelining stages for the first 10 instructions of a program. Assume that Instruction-4 is a conditional loop instruction. If the condition is TRUE, CPU runs instructions: 7 - 9 twice. Please note that a single-port RAM is used with the system, such that CPU read only one data from RAM or save only one data to RAM at a time. Calculate the execution time for the first 10 instructions of a program as well. b) Show the time steps and calculate the execution time for above problem while a multiport RAM is used with the system.

Make sure to find the following: Total (actual) time: Time wasted: % Wasted: