APPENDIX B - Verilog Module module vmc (| parameter s0-2'b00, s1=2'b01, s2=2'b10; reg state; reg P, R; initial begin state=s0; P=0; R#0; end alwayse (posedge clk) begin if(reset) begin state=s0; P=0; R=0; end else begin case (state) s0: if(D) begin state-s1; Pw0; R=0; end else if (C) begin state-s2; P=0; R=0; end else begin state-s0; P=0; R=0; end s1: S2 : endcase end end
APPENDIX B - Verilog Module module vmc (| parameter s0-2'b00, s1=2'b01, s2=2'b10; reg state; reg P, R; initial begin state=s0; P=0; R#0; end alwayse (posedge clk) begin if(reset) begin state=s0; P=0; R=0; end else begin case (state) s0: if(D) begin state-s1; Pw0; R=0; end else if (C) begin state-s2; P=0; R=0; end else begin state-s0; P=0; R=0; end s1: S2 : endcase end end
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
Related questions
Question
Transcribed Image Text:You are hired by CurryPapa company to design a curry puff vending machine controller.
The price of a curry puff is 30¢. The machine has a single coin slot that only accepts 10¢
and 20¢ coins. The size of the coin slot is designed such that only one coin can be inserted
at a time. A mechanical sensor indicates whether a 10¢ coin or a 20¢ coin has been inserted
into the coin slot. The machine delivers a curry puff to the customer after it has received
total 30¢ coins. If the machine received total 40¢ coins, it delivers a curry puff and returns
a 10¢ coin as the change.
(b)
The company also asked you to design the vending machine controller using
Verilog. Complete the Verilog module in Appendix B by writing proper codes in
the empty boxes.
Transcribed Image Text:APPENDIX B - Verilog Module
module vmc (
);
parameter s0=2'b00, s1=2'b01, s2=2'b10;
reg
state;
reg P, R;
initial begin
state=s0; P-=0; R=0;
end
alwayse (posedge clk) begin
if (reset) begin
state=s0; P=0; R=0;
end
else begin
case (state)
so: if (D) begin
state-sl; P=0; R=0;
end
else if (C) begin
state=S2; P=0; R=0;
end
else begin
state=s0; P=0; R=0;
end
s1:
s2:
endcase
end
end
Expert Solution
This question has been solved!
Explore an expertly crafted, step-by-step solution for a thorough understanding of key concepts.
Step by step
Solved in 3 steps with 1 images
Recommended textbooks for you
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Concepts of Database Management
Computer Engineering
ISBN:
9781337093422
Author:
Joy L. Starks, Philip J. Pratt, Mary Z. Last
Publisher:
Cengage Learning
Prelude to Programming
Computer Engineering
ISBN:
9780133750423
Author:
VENIT, Stewart
Publisher:
Pearson Education
Sc Business Data Communications and Networking, T…
Computer Engineering
ISBN:
9781119368830
Author:
FITZGERALD
Publisher:
WILEY