an 8x1 multiplexer using only 74LS153 and 74LS157. Show Pin connections for your design.

You are requested to design 16 x 1 multiplexer, meaning that this combinational circuit has 16 data inputs and produces a single output using selection bits. How many selection bits require?   Question 5 options: - 4 - 5 - 2 - 3

Provide an Explanation!

The 16-bit FCLA taught in class features a two-level design, i.e. level 1: use pi and gi signals to calcuate super signals, and level 2: use super signals Pi and Gi to calculate the carryout from the MSB. Now consider using FCLA to support 256-bit additions. How many levels will there be in your design? Why? Using gate delay as the unit of time, how many gate delays are needed for your 256-bit adder to output the carryout from its MSB?