Database System Concepts
7th Edition
ISBN: 9780078022159
Author: Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher: McGraw-Hill Education
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- Suppose we have a byte-addressable computer using direct mapping with 16-bit main memory addresses and 32 blocks of cache. If each block contains 8 bytes. a. Determine the number of bits of the tag field. b. To which cache block would the hexadecimal address 0x2468 map? c. What is the tag of the hexadecimal address 0x2468arrow_forwardSuppose a computer using fully associative cache has 224 words of main memory and a cache of 512 blocks, where each cache block contains 16 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? To which cache block will the memory reference 17042416 map?arrow_forwardA microprocessor with 32-bit address bus has an on-chip 16-KByte four-way set-associative cache memory, the line size is 4 bytes. Draw a block diagram of this cache showing its Organization and how the different address fields are used to determine a cache hit/miss. Where in the cache is the word from memory location ABCDE8F8 mapped?arrow_forward
- Cache system B represents a 2-way set-associative mapping cache system in table 2 The system is byte-addressable and the block size is one word (4 bytes). The tag and set numbers are represented with binary numbers. The contents of words in a block are represented with hexadecimal. Tag 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 Table 2 1. What is the size of the main memory for the Cache system B? Answer= 2. What is the size of the cache memory of Cache system B? Answer = Answer= Answer = 16 Answer = Set Number 16 1011 0110 1101 1011 0110 1101 miss(es) 1011 0110 1110 1011 0110 1110 1011 0110 1111 1011 0110 1111 1011 0111 0000 3. If we request to read memory address F1 24 2D B7, what data do we get? 1011 0111 0000 1011 0111 0001 1011 0111 0001 4. If we…arrow_forwardYou are given a main memory of 64Mbytes with each byte addressable and asked to design a cache memory using direct mapping. The main memory is organized as blocks of 8bytes. The cache memory must have a size of 512Kbytes. How many lines do you need to use in the cache memory?arrow_forwardFor a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. Tag Index Offset 63-10 9-5 4-0 (A) What is the cache block size (in words)? (B) How many blocks does the cache have? (C) What is the ratio between total bits required for such a cache implementation over the data storage bits?arrow_forward
- Consider a 32-bit physical memory space and a 32 KiB 2-way associative cache with LRU replacement. You are told the cache uses 5 bits for the offset field. Write in the number of bits in the tag and index fields. Tag length in bits = Index length in bits =arrow_forwardConsider a cache with 64 blocks and a block size of 16 bytes. To what block number does byte address 1200 map?arrow_forward
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