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- Write a VHDL code for the following simple logic circuit. D- X1 X2 f X3A three input logic functipn will provide a logic high output only when twp (and two only) of the inputs are logic highs. For all other input possibilities, a logic zero is provided on the output. What is the logic expression? A. Y=A'B'C+A'BC'+AB'C' B. Y=AB'C+A'BC+ABC' C. Y=AB'C+ABC+A'B'C' D. Y=ABC'+AB'C+A'B'C'mybmsajmanac ERSITY Design My courses Logic Design General Qua 2 LD/DLD on Tue. 7/12/21-Dr. Zidan The correct state sequence of the cirtut with initial state Qo1, 01 and Q0 D. Q D, a. LSB MSB Clock Select one O a1, 2, 5.3, 7,6,4 O b.1,6, 5,7, 2.3,4 O C1,2.7,3, 5,6, 4 O d 1,3,4, 6, 7,3.2
- 3Draw the state table and state graph for fhe following logic cirad A CLKReset A/O B/O so S1 S2 B/O AB/1 A/O A+ BIO Describe in words what the state machine in figure above does. Using one- hot encodings, complete a state transition table and output table for the FSM above. Write Boolean equations for the next state and output and sketch a schematic of the FSM.Design a JKFF by using only a DFF and logic gates. Please design on logisim or handwriting
- Q2/A. Design a logic circuit that perform the following Boolean function, use 4-to-1 multiplexer and other logic gates you may need in the design. Use Shannor expansion 21 18 31 f(A, B, C, D, E) = ABCDE + ABCDE + ABCDE + ABCDE %3D l68421 B. Design 8-bit Adder/Subtracter using 4-bit Adder and 2-to-1 multiplexers other logic gates you may need in the design.Design a code converter that converts a decimal digit from BCD to excess-3 code, the input variables are organized as (A BC D) respectively with A is the MSB, the output variables are organized as (W X Y Z) respectively with W is the MSB, put the invalid decimal numbers as don't care. X= BCD'+B'D+B'C X= BC'D'+B'D+BC X= BC'D'+B'D+B'C X= BC'D'+BD+B'CSimplify the following expression using Karnaugh map and implement. Draw simplified logic diagram as well. Implement on Multisim software. (a) Y=A.B.C'.D+A.B'.C'.D+A'.B'.C'.D+A'.B.C'.D+A'.B'.C'.D'+A'.B.C'.D'+A'.B.C.D'+A'.B.C.D+A'.B'.C.D
- Perform floating point binary addition to the following: A: 1 10000011 10110111010000000000000 B: 0 10000000 10010011000100101000000 The result of A+B must be in be in 32-bit floating point. You can also check the answer in decimal.USE DIGITAL LOGIC AND DESIGN Part 1: In Figure_4; we have 4-bit Comparator using 2-bit Comparators block. You have to satisfy given condition by applying all data on figure 4. At the end, given condition should produce HIGH output and other two should be LOW. A3 A2 A1 A0 = 1101 and B3 B2 B1 B0 = 1110 Figure_4 Part 2: The serial data-input waveform (Data in) and data-select inputs (S0 and S1) are shown in Figure_5. Determine the data-output waveforms from D0 through D3. Figure_5 Part 3: Decoder can be useful when we have to decode some specific numbers from their equivalent code. Figure 6 has a concept of 3 to 8 line decoder from which you have to generate output waveform from D0 to D7 with proper relationship to input. Figure_6 Part 4: The data-input and…A circuit for adding two 3-bit 2's complement numbers (X2X1Xo and Y2Y1Y0) that uses Full Adder (FA) components is shown below. Write the full logic expression to detect overflow. Cout C3 X₂X₁ Xo FA Cir Cout C₂ Cout FA C S Z₂ Z₁ (Y₂) (Y₁ Yo Zo C₁ Cout FA Cin