7- The inclusion property that requires checking only last-level caches for coherence transactions is: A-Inclusive B-Non-inclusive C- Exclusive D- (B and C) 8- In MSI coherence protocol, one of the following states also implies that the cache block exists in only one of the caches in the system: B-Shared C- Dirty D- (None) 9- Assume we have a single-level cache hierarchy system that runs an application. If you know that L1 cache hit time is 5 cycle, hit rate is 55% and memory latency is 100 cycles. The AMAT is: A-14.5 B-60 C- 5.55 A-Modified D-50
7- The inclusion property that requires checking only last-level caches for coherence transactions is: A-Inclusive B-Non-inclusive C- Exclusive D- (B and C) 8- In MSI coherence protocol, one of the following states also implies that the cache block exists in only one of the caches in the system: B-Shared C- Dirty D- (None) 9- Assume we have a single-level cache hierarchy system that runs an application. If you know that L1 cache hit time is 5 cycle, hit rate is 55% and memory latency is 100 cycles. The AMAT is: A-14.5 B-60 C- 5.55 A-Modified D-50
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Answer 7,8 and 9 please
![T-Mobile
A-14.5
A- Refresh
6:29 PM
Today
6:08 PM
1- Emerging NVMs are expected to replace DRAM because of their:
A-Density/Capacity B-Low power C-Speed
D- (A and B)
2- The DRAM operation that is required to adjust the bitlines' voltage before
read/write operation is called:
B- Precharge
3- To mitigate control hazards, processor cores use:
A- Prefetching B-Branch delay slots C- Branch prediction D- (B and C)
4- Which of the following data hazards can cause stalls in in-order pipelines:
A-Read-After-Read B-Write-After-Read C-Read-After-Write D- (None)
5- For the same cache size, increasing cache associativity reduces:
A-Capacity misses B-Conflict misses C-Cold misses D- (All Answers)
6- For a fully-associative cache, increasing cache size reduces:
A- Capacity misses B-Conflict misses C- Cold misses D- (All Answers)
7- The inclusion property that requires checking only last-level caches for
coherence transactions is:
A-Inclusive
B-Shared
C-Activation D- Interleaving
B- Non-inclusive C- Exclusive
D- (B and C)
8- In MSI coherence protocol, one of the following states also implies that the
cache block exists in only one of the caches in the system:
A- Modified
C- Dirty
D- (None)
9- Assume we have a single-level cache hierarchy system that runs an
application. If you know that L1 cache hit time is 5 cycle, hit rate is 55% and
memory latency is 100 cycles. The AMAT is:
B-60
C- 5.55
@ 100% 2
D-50
y requase the studieAR) dep
ommit
i
Edit
EP](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F0a997a6f-a222-4716-adb9-ab223c542cab%2Fd60991e5-6e2b-48ee-811d-a021d5e7d20f%2Fdjgmum_processed.jpeg&w=3840&q=75)
Transcribed Image Text:T-Mobile
A-14.5
A- Refresh
6:29 PM
Today
6:08 PM
1- Emerging NVMs are expected to replace DRAM because of their:
A-Density/Capacity B-Low power C-Speed
D- (A and B)
2- The DRAM operation that is required to adjust the bitlines' voltage before
read/write operation is called:
B- Precharge
3- To mitigate control hazards, processor cores use:
A- Prefetching B-Branch delay slots C- Branch prediction D- (B and C)
4- Which of the following data hazards can cause stalls in in-order pipelines:
A-Read-After-Read B-Write-After-Read C-Read-After-Write D- (None)
5- For the same cache size, increasing cache associativity reduces:
A-Capacity misses B-Conflict misses C-Cold misses D- (All Answers)
6- For a fully-associative cache, increasing cache size reduces:
A- Capacity misses B-Conflict misses C- Cold misses D- (All Answers)
7- The inclusion property that requires checking only last-level caches for
coherence transactions is:
A-Inclusive
B-Shared
C-Activation D- Interleaving
B- Non-inclusive C- Exclusive
D- (B and C)
8- In MSI coherence protocol, one of the following states also implies that the
cache block exists in only one of the caches in the system:
A- Modified
C- Dirty
D- (None)
9- Assume we have a single-level cache hierarchy system that runs an
application. If you know that L1 cache hit time is 5 cycle, hit rate is 55% and
memory latency is 100 cycles. The AMAT is:
B-60
C- 5.55
@ 100% 2
D-50
y requase the studieAR) dep
ommit
i
Edit
EP
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