5. Schedule the project using 2 processors and the critical-path priority list. Show the Gantt chart. T7 THI 8 (12) T₁ 15 TA 5 T₂ (18) T3 5 T6 (12) (25) Ts 5 T8 5 T10 (60) T9 I
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- Stella designs a 3 GHz processor where two important programs, A and B, take one second each to execute. Each program has a CPI of 1.5. Sam is tasked with designing the company's next-generation processor and she comes up with an idea that improves the CPI of A to 1.25 and the CPI of B to 1. But the processor can only be implemented with a cycle time of 0.5 ns. Does Sam's new processor out-perform Stella's processor on program A? How about on program B?As newly hired test engineers in a semiconductor company, your team is tasked to test a new lab sample series of microprocessors, which will be mass manufactured after the management's go signal. • Your team noticed that 3 out of 10 microprocessor has faulty registers. • The new series of processors will be in the team's hand whether it will be dispatched or not. • Your team initiated telling the supervisor about it. The supervisor tasked the team to do the following: • Engage with your team and brainstorm solutions that would cater to this scenario. • Write a one-page detailed report on the status of the lab microprocessors. o The report template should follow IEEE General Format. o Point-out the problems that will incur if the sample microprocessors will be dispatched. Pinpoint the involved departments that caused this situation. o Suggest an innovative approach and solution in dealing with this scenario. o Determine process/es which can be improved in terms of fabrication and…Let us consider the performance of two ARM processors executing the same program to completion. The program has 1 million instructions. - Processor A, produced by Qualcomm, has a clock rate of 1.5 GHz, and has an average CPI for the given program of 2.70. |- Processor B, produced by Samsung, has a clock rate of 2.2 GHz, and has an average CPI for the given program of 1.79. What is the speed up of Processor A with respect to Processor B? Note round your answer to the second decimal place (e.g. 1.01).
- Question: Suppose a program of 600 instructions runs on a 2 GHz processor. The frequency of instructions and the clock cycle counts per instruction are given as follows. What is the average CPI of this instruction mix? Operation Frequency Clock Cycles ALU operations 55% 1 Loads/Stores 30% 2 Branches 15% 3 Question: Continue from the previous question. What is the CPU time of the program in nanoseconds? Question: Suppose a processor P has a 2.5 GHz clock rate and a CPI of 1.5. If the processor executes a program in 3 microseconds, find the number of instructions in the program.A benchmark program to evaluate the performance of a processor spends 80% of its time on floating-point commands and 20% on non-floating point commands. A design team wants to obtain an overall speedup of 40% over the existing run time of this benchmark program by speeding up ONLY the non-floating point commands. What should be the ratio of the non-floating point commands new runtime to that of its old runtime? Select the best answer. This is a trick question! In this scenario, it is impossible to speed up only the non-floating point commands to obtain an overall 40% speedup! 2 0.5 2.5Explain the concept of dynamic multithreading in processor architecture. How does it differ from simultaneous multithreading (SMT), and what are the performance benefits?
- Suppose we had a processor design with 5 stages where each stage takes the following amount of time: IF: 400 ps ID: 200 ps EX: 300 ps MEM: 500 ps WB: 200 psQ1: If you choose a pipelined design, what is the CPI? Assume that we have enough instructions such that the brief ramp up period at the beginning and the ramp down period at the end with less than 100% utilization does not matter. Q2: If you choose a pipelined design, what is the average execution time per instruction in picoseconds?As a computing expect, your expertise is required to evaluate the potential performance of two new processors, each implementing a different ISA. The evaluation is based on its performance on a particular benchmark. On the processor implementing ISA A, the best compiled code for this benchmark performs at the rate of 12 IPC. That processor has a 660 MHz clock. On the processor implementing ISA B, the best compiled code for this benchmark performs at the rate of 4 IPC. That processor has a 800 MHz clock. a) What is the performance in MIPS (millions of instruction per sec) of the processor implementing ISA A? b) What is the performance in MIPS (millions of instructions per sec) of the processor implementing ISA B? c) Which is the higher performance processor? d) Explain your answer in c) abovePlease explain how prioritizing the I/O queue above the process execution queue might improve performance. If the I/O is interrupted, who knows what will happen. To what extent this will reduce the maximum burst rate of the CPU is unclear. I don't think I understand what you're getting at.
- The shift from serial to parallel processing is the most important, in your opinion. Think about why this is a good idea and back it up with solid arguments?Let there are three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3.3 GHz clock rate and a CPI of 1.6. P2 has a 2.8 GHz clock rate and a CPI of 1.2. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. a. Which processor has the highest performance expressed in instructions per second? b. If the processors each execute a program in 9 seconds, find the number of cycles and the number of instructions. c. We are trying to reduce the execution time by 33°%, but this leads to an increase of 22% in the CPI. What cłock rate should we have to get this time reduction?The arrival time for processes A,B,C and D is 0,2,4, and 5 while the required CPU burst time is 7,4,1 and 4 respectively. Using SRTN, what is the average turn-around time?