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- Q.8 Determine the Q waveform relative to the clock if the signals shown in Figure 03 are applied to the inputs of the J-K flip-flop. Assume that Q is initially LOW. CLK K PRE CLK CLR K FIGURE 03Design a Up Down Counter by using JK flip flop and verify the output of your designed circuit onany random input. Provide the following information as well:1. State table2. State diagram3. State equations4. Complete circuit diagram9 Two edge-triggered J-K flip-flops are shown in The Figure. If the inputs are as shown, draw the Q output of each flip-flop relative to the clock, and explain the difference between the two. The flip-flops are initially RESET. CLK CLK-C CLK C K (a) (b)
- 5. The circuit below contains a gated D latch and a JK flip-flop. Complete the timing diagram by drawing the waveforms for X and Z. Assume initial values X = Z = 0. C A X Z D G Q X CK K Q Zlulaial X Meel ixd ovyv ke xprx zh8NaCiqWSsG-ntxcCe_c83_6 h5cMyyKtw/formResponse News what is the advantage of the following circuit y What is the type of the flip flop? Why? Next state Present state output output delayhbkxprx_zh8NaCiqWSsG-ntxcCe_c83 6J-h5cMyyKtwA/formResponse News What is the type of the flip flop? Why? O. Google z-- LS J-U elaYI se land E E Ninevah University J E Google 10
- show the waveforms for each flip-flop output with respect For the ring counter in Figure to the clock. Assume that FF0 is initially SET and that the rest are RESET. Show at least ten clock pulses. D D. FFO FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 FP9 CLKDesign the circuit of the following synchronous counter defined by the state transition diagram. Show the state table, the simplified K-Map and Boolean equation of each input and draw the circuit. Use JK flip flop. 000 001 111 010 110 101 011 100Design a synchronous counter using JK flip flop for the following sequence. 000,101,110,111,011,010 explain in detail
- Q3 13. Determine how the microcell is configured (combinational or registered) and the data bit that is on the output (to I/O) for each of the following conditions. The flip-flop is a D type. ܠܐ ines PLA 15 expander product terms from other macrocells Product term selection matrix Shared expander Parallel expanders from other macrocells Global Global clear clock MUX 2 Vcc MUX 1 MUX 3 MUX 4 PRE DIT C EN CLR Q MUX 5 From I/O To I/OD. Design a sequential circuit with eight (8) states and the state transitions are defined in the table shown below. (a) Derive the state table with JK flip-flop inputs using the JK flip-flop excitation table. (b) Derive the JK flip-flop input equations. Present State a b C d h Next State x = 0 8 d f 8 x = 1 b C e a C b h a Output x = 0 0 0 0 1 0 1 x = 1 0 0 0 0 0 1 0Design a combinational circuit using multiplexer for a car chime based on thefollowing system: A car chime or bell will sound if the output of the logic circuit(X) is set to a logic ‘1’. The chime is to be sounded for either of the followingconditions:• if the headlights are left on when the engine is turned off and• if the engine is off and the key is in the ignition when the door is opened.Use the following input names and nomenclature in the design process:• ‘E’ – Engine. ‘1’ if the engine is ON and ‘0’ if the engine is OFF• ‘L’ – Lights. ‘1’ if the lights are ON and ‘0’ if the lights are OFF• ‘K’ – Key. ‘1’ if the key is in the ignition and ‘0’ if the key is not in the ignition• ‘D’ – Door. ‘1’ the door is open and ‘0’ if the door is closed• ‘X’ – Output to Chime. ‘1’ is chime is ON and ‘0’ if chime is OFF