22. Determine the radix r for the case: (87)10=(153),. A.9 B.8 C.7 D.6 E. 5

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Determine the radix r for the case:

The circuit below is called__________.

Full adder forms _________________________, but half-adder forms ___________________.

The truth table for AND gate is:

14 pin TTL SSI chip can contain ___________ 3 input AND gates.

Canonical form of a function’s representation can give us its _______ level implementation.  

22. Determine the radix r for the case: (87)10=(153),. A.9 B.8
C.7 D.6 E. 5
23. The circuit below is called
A. 2*4 decoder
B. 2*4 decoder /DUX
C. priority encoder D. 4-input
priority encoder E. 4-bit adder-subtractor
FA
FA
FA
FA
Ga
Se
24. Full adder forms
forms
but half-adder
A. the sum of two bits, .... the sum of two bits and a previous
carry.
B. the sum of two bits, .... the sum of two bits and a carry
C. the sum of two bits, .... the sum of two bits and a present carry
D. the sum of two bits and a carry,... the sum of two bits
E. the sum of two bits and a previous carry, ... the sum of two bits
25. The truth table for AND gate is:
A || B
D || E
xly F x]yF xly F xyF x\y F
|111101|01010|00이1| |11|1| |010101
|0110 |0111||0이1|1||0110| |011|
100101
ol0111
o0101
D00 110
10
26. 14 pin TTL SSI chip can contain
gates.
А. 1
27. Canonical form of a function's representation can give us its
3 input AND
В. 2
С.3
D. 4
Е. 5
level implementation.
А. 1
В. 2
C. 1 or 2
D. 3
E. 2 or 3
Transcribed Image Text:22. Determine the radix r for the case: (87)10=(153),. A.9 B.8 C.7 D.6 E. 5 23. The circuit below is called A. 2*4 decoder B. 2*4 decoder /DUX C. priority encoder D. 4-input priority encoder E. 4-bit adder-subtractor FA FA FA FA Ga Se 24. Full adder forms forms but half-adder A. the sum of two bits, .... the sum of two bits and a previous carry. B. the sum of two bits, .... the sum of two bits and a carry C. the sum of two bits, .... the sum of two bits and a present carry D. the sum of two bits and a carry,... the sum of two bits E. the sum of two bits and a previous carry, ... the sum of two bits 25. The truth table for AND gate is: A || B D || E xly F x]yF xly F xyF x\y F |111101|01010|00이1| |11|1| |010101 |0110 |0111||0이1|1||0110| |011| 100101 ol0111 o0101 D00 110 10 26. 14 pin TTL SSI chip can contain gates. А. 1 27. Canonical form of a function's representation can give us its 3 input AND В. 2 С.3 D. 4 Е. 5 level implementation. А. 1 В. 2 C. 1 or 2 D. 3 E. 2 or 3
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