2.1 A benchmark program is run on a 40 MHz processor. The executed program consists of 100,000 instruction executions, with the following instruction mix and clock cycle count: Instruction Type Instruction Count Cycles per Instruction Integer arithmetic 45,000 1 Data transfer 32,000 Floating point 15,000 2 Control transfer 8000 2 Determine the effective CPI, MIPS rate, and execution time for this program. 2)

2. If a microprocessor has a cycle time of 0.3 nanoseconds, cons, has the processor dock at the fetch cycle is 30% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait stales)

A computer system contains a big endian byte addressable memory system with 8 separate memory modules. Each memory module is 32 bits wide and contains 134217728 cells. Cells within each memory module are numbered 0 through 134217727. a) If the memory employs high order interleaving, what is the 32-bit memory address of cell 1048578 within module 3? b) If the high order interleaved memory uses little-endian instead of big-endian storage order, what is the 32-bit memory address of cell 511 within module 1? c) If the memory employs low order interleaving, what is the 32-bit memory address of byte 1048575 within module 2? Bytes are numbered starting from 0. Express the address in hex. d) What is the main advantage of using low-order interleaved memory compared to using high-order interleaved memory?

You are given an instruction set architecture (ISA) with a variable-length instruction encoding scheme and instruction categories for a test program as tabulated in Table 1. Table 1: Instruction Categories and Encoding Scheme Instruction Length (bits) Instruction Category Frequency 40% 24 ALU operations Loads Stores 32 32 20% 20% 20% 16 Branches A. Compute the average instruction length (AIL) for the variable-length instruction encoding scheme in Table 1. B. Compute the memory storage requirements (in bytes) for the test program under the variable-length instruction encoding scheme (Table 1) if it contains 1 billion (i.e., 1 x 10º) instructions. C. Compute the memory savings (as a percentage) compared to a baseline fixed-length instruction encoding scheme with 32 bits per instruction for the test program with 1 billion (i.e., 1 x 10°) instructions.