2. Realize the following function F;(4, B,C, D) = E(1, 2, 5, 6, 7, 11) т using a (a) 4-to-1 multiplexer, and draw the logic diagram. (b) 8-to-1 multiplexer, and draw the logic diagram. You may use external gates if needed.
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- For the logic diagram shown in Figure 2, find logic function Q prove it is equivalent to Ex-NOR gate. i. A- DDO BSelect a suitable example for for combinational logic circuit. O a. None of the given choices O b. De-multiplexer O c. PLA O d. LatchesThe numbers from 0-9 and a no characters is the Basic 1 digit seven segment display * .can show False True In a (CA) method of 7 segments, the anodes of all the LED segments are * "connected to the logic "O False True Some times may run out of pins on your Arduino board and need to not extend it * .with shift registers True False
- Q2/A) Design 8x1 multiplexer using 2x1 multiplexer? Q2 B)Simplify the Logic circuit shown below using K-map then draw the Simplified circuit? Q2/C) design logic block diagram for adding 12 to 5 using full adder showing the input for each adder?Electrical Engineering 3. For the logic circuit in Figure 1, compute the following parameters: A) The total number of single stuck-at faults. B) The total number of all possible multiple stuck-at fault combinations. C) The total number of stuck-open faults. Note: You can assume that 3-input AND gate is realized using 8 transistors, a two-input OR gate is realized using 6 transistors, and an inverter is realized using 2 transistors.Q/ What are the domains of logic gates?
- Q/What are the uses of logic gates?(c) Figure Q3(c)(i) shows a register and Figure Q3(c)(ii) shows the input waveforms (CLOCK and Data in) to the circuit. A1 A9 A10 A2 Function generator A3 A11 A12 AS A13 A6 A14 A7 A15 Data in Bop.7) ip.r 82p.7) Logic analyser U1 U2 U3 U4 UO 6. 1. 6 1 6 INVERTER 3 CLK 3 CLK oCLK CLK 5 K K 5 K K 4027 Clock Function generator Figure Q3(c)(i) (i) Determine the type of register as shown in Figure Q3(c)(i).Q/What is the importance of logic gates?
- 9 Part 1 of 2 Mc Graw Hill Required information Consider the logic gate circuit shown in the given figure. A (S1)-0- B (S2)-0 C (S3)-0- AB B BC B+C What is the Boolean equation for the given figure? ***************** The Boolean equation for the given figure is (Click to select) Note: This is a multi-part question. Once an answer is submitted, you will be unable to return to this part.Draw the output waveform C and D, given the input waveforms A and B as shown belowfigure 2.Figure 2b) Verify the result from part (a) by any using simulation tools. (Screen shoot only for thefollowing input cases: when (A=0, B=0), (A=1, B=0) and (A=0, B=1). c) For the logic circuit given in Figure 3, obtain the output expression for ?d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.