2. Consider the following: (a) Design a 4 to 1 multiplexer using transmission gates such that the digital inputs are A, B, C, D and the control (or select) inputs are So and S₁. (b) Implement the function Y CMOS circuit tonology = (A+B+C + D) · (E+F+G) · (H + I) using Domino . .
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- (i) Below (figure 1) is an example of a VHDL code for a multiplexer. --multiplexer.vhd --Common Multiplexer LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY multiplexer IS PORT(el, d3, d2, d1, d0 : IN STD_LOGIC; a,b.c,d,e,f.g.h.ij.k,lm,n:OUT STD LOGIC); END multiplexer; ARCHITECTURE mult OF multiplexer IS SIGNAL input : STD LOGIC_VECTOR (4 downto 0); SIGNAL output : STD LOGIC_VECTOR (13 downto 0); BEGIN input ca el & d3 & d2 & d1 & d0; WITH input SELECT "00000010000001"WHEN "10000",--Input A "00000010000001"WHEN "10001",- "00000010000001"WHEN "10010",- "00000010000001"WHEN "10011",- "00000011001111"WHEN "10100" "00000011001111"WHEN "10101 "00000011001111"WHEN "10110" "00000011001111"WHEN "10111" "10011110000001"WHEN "11000" "10011110000001"WHEN "11001" "10011110000001"WHEN "11010, "10011110000001"WHEN "11011" "10011111001111"WHEN "11100" "100111110011i1"WHEN "11101",- "10011111001111"WHEN "11110",-- "10011111001111"WHEN "11111":-. "00000010000001" -00 --"00000011001111"-01…We want to design a digital circuit that converts Gray code (ABC) to Binary code (xyz). Set up a 8-to- 1 line multiplexer so that the output gives y as a function of ABC. "A" is given to the most significant bit of the control inputs of the multiplexer. "C" is given to the least significant bit of the control inputs of the multiplexer.Q2: In the 7-segment display, derive an SOP expression for segment ('f )'using the input variables WXYZ and theń expression using Karnaugh map (each digit represented by a BCD codě). minimize the
- Please consider the digit ( dU5148 ). Print that specific combination using one 7 segment display in a serial. the following should be included in the report. 1. Generalized Equations (SOP & POS).4. A data signal with bipolar voltage levels is shown below. The decision threshold is 0 volts. The logic levels are +1 volt for logic 1 and -1 volt for logic 0. Noise with the P.D.F. shown corrupts the signal. Find the probability of error at some instant of time on the condition that logic 0 is sent. LOGIC 1 +1 VOLT -2 1/2 دمت ~IN kla THRESHOLD +2 NOISE P.D.F. -I VOLT. LOGIC 0(b) Figure Q.4b shows an Adder/Subtractor circuit implemented using Adder Q. The delay for XOR = 2t, OR = AND=1t and cascadable full adder is used for ripple carry adder. Assume inputs X, Y and ADDSUB have arrived at Ot. Analyze the critical path delay for the circuit if:- X[7.4] YI7.4] 4. A[3.0] A[3.0] lo"cle C4 C8 C4 Adder Q co C4 Adder Q co ADDSUB Sum(3.0] Sum[3.0] Z17.4] Figure Q.4b i. Adder Q is a 4-bit Ripple-Carry Adder. Show your analysis in Table Q.4b.i. ii. Adder Q is a 4-bit Carry-Lookahead Adder. Show your analysis in Table Q.4b.ii. Table Q.4b.i Table Q.4b.ii To Node Delay To Node Delay Z3 Z3 С4 С4 Z7 Z7 C8 C8 Page 14 of 21
- Hello please solve this problem using the KVL and KCL method. This is from the 6th edition of NISE control systems engineering, Thank you very much.Implement 8-bit asynchronous ripple counter and showing truth table, timing diagram. Also show how it can be used as frequency divider?Give the Answers of following questions, 1: without reducing implement the following Boolean expression using basic gatesY Y= (A' B)'+A+BC 2: Reduce the following Boolean expression using Boolean algebra. Y = (A+BC)' (AB'+ (ABC)') 3: Explain the construction and working of the Depletion MOSFET, with characteristics curve.