(b) Figure Q.4b shows an Adder/Subtractor circuit implemented using Adder Q. The delay for XOR = 21, OR = AND=1t and cascadable full adder is used for ripple carry adder. Assume inputs X, Y and ADDSUB have arrived at Ot. Analyze the critical path delay for the circuit if:- B3.0] C4 C4 Adder Q co C4 Adder Q co ADDSUB Sum[3.0] lorcluns Figure Q.4b i. Adder Q is a 4-bit Ripple-Carry Adder. Show your analysis in Table Q.4b.i. ii. Adder Q is a 4-bit Carry-Lookahead Adder. Show your analysis in Table Q.4b.ii. Table Q.4b.i Table Q.4b.ii To Node Delay To Node Delay Z3 Z3 C4 C4 Z7 27 C8 C8
(b) Figure Q.4b shows an Adder/Subtractor circuit implemented using Adder Q. The delay for XOR = 21, OR = AND=1t and cascadable full adder is used for ripple carry adder. Assume inputs X, Y and ADDSUB have arrived at Ot. Analyze the critical path delay for the circuit if:- B3.0] C4 C4 Adder Q co C4 Adder Q co ADDSUB Sum[3.0] lorcluns Figure Q.4b i. Adder Q is a 4-bit Ripple-Carry Adder. Show your analysis in Table Q.4b.i. ii. Adder Q is a 4-bit Carry-Lookahead Adder. Show your analysis in Table Q.4b.ii. Table Q.4b.i Table Q.4b.ii To Node Delay To Node Delay Z3 Z3 C4 C4 Z7 27 C8 C8
Electricity for Refrigeration, Heating, and Air Conditioning (MindTap Course List)
10th Edition
ISBN:9781337399128
Author:Russell E. Smith
Publisher:Russell E. Smith
Chapter17: Commercial And Industrial Air-conditioning Control Systems
Section: Chapter Questions
Problem 25RQ
Related questions
Question
![(b) Figure Q.4b shows an Adder/Subtractor circuit implemented using Adder Q. The delay for
XOR = 2t, OR = AND=1t and cascadable full adder is used for ripple carry adder. Assume
inputs X, Y and ADDSUB have arrived at Ot. Analyze the critical path delay for the circuit
if:-
X[7.4]
YI7.4]
4.
A[3.0]
A[3.0]
lo"cle
C4
C8
C4
Adder Q
co
C4
Adder Q
co
ADDSUB
Sum(3.0]
Sum[3.0]
Z17.4]
Figure Q.4b
i. Adder Q is a 4-bit Ripple-Carry Adder. Show your analysis in Table Q.4b.i.
ii. Adder Q is a 4-bit Carry-Lookahead Adder. Show your analysis in Table Q.4b.ii.
Table Q.4b.i
Table Q.4b.ii
To Node
Delay
To Node
Delay
Z3
Z3
С4
С4
Z7
Z7
C8
C8
Page 14 of 21](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F6a30be74-a81e-4985-b94d-4cd71e619e2d%2F2198ebcd-7566-4ab1-b2b2-6893783d8f50%2Fwaegks_processed.jpeg&w=3840&q=75)
Transcribed Image Text:(b) Figure Q.4b shows an Adder/Subtractor circuit implemented using Adder Q. The delay for
XOR = 2t, OR = AND=1t and cascadable full adder is used for ripple carry adder. Assume
inputs X, Y and ADDSUB have arrived at Ot. Analyze the critical path delay for the circuit
if:-
X[7.4]
YI7.4]
4.
A[3.0]
A[3.0]
lo"cle
C4
C8
C4
Adder Q
co
C4
Adder Q
co
ADDSUB
Sum(3.0]
Sum[3.0]
Z17.4]
Figure Q.4b
i. Adder Q is a 4-bit Ripple-Carry Adder. Show your analysis in Table Q.4b.i.
ii. Adder Q is a 4-bit Carry-Lookahead Adder. Show your analysis in Table Q.4b.ii.
Table Q.4b.i
Table Q.4b.ii
To Node
Delay
To Node
Delay
Z3
Z3
С4
С4
Z7
Z7
C8
C8
Page 14 of 21
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