2) Construct a mod-7 counter using universal counter a) count sequence "0,1,2,3,4,5,6" b) "9,10,11,12,13,14,15" c) "3,4,5,6,7,8,9"

a) Design a synchronous Divide-by-10 UP Counter using T flip-flop, following the steps of designing sequential circuits. b) For the shift register circuit shown in Figure 2, write the outputs at Q, Q, Q, and Q, for each clock pulse (for 4 clock pulses) in the form of a table. D DE Clock Figure 2 ol to lol ol

4. Design a 1-bit Full adder using one 3-bit majority encoder and a set of NAND gates (Design: means all the steps)

3(a): Consider the following circuit, which uses two D flip-flops with falling edge triggers along with -bit full adder. The flip-flops are controlled by a single clock, C.  Suppose C, Q0 and Q1 all initially have the value 0. First, fill in the blanks in the "i " = 0 (initial state)" row to show the values of D0 and D1  at this initial time (assume the results of the adder have had time to stabilize) . Next, show the values of Q0 , Q1, D0 , and D1 once they have stabilized after the ith falling edge of the clock, where i ranges from 1 to 4. Note that both the A and Carry In inputs of the adder are (Q not ) Q'0 not Q0 None of these first four rows should be the exactly the same.