[15] For a direct mapped cache design with 32-bit address, the followingbits of the address are used to access the cacheTag31-10IndexOffset9-43-0A. Assuming a direct mapped cachea. What is the cache block size?b. What is the cache size?c. How many entries/sets/rows does the cache have?d. Starting from power on, the following byte addressed cachereferences are recorded:4,16, 5,4,6, 12Compute the hit ratio for this sequence of addresses.B. Answer above questions assuming the cache to be a 4-way setassociative cache.

A. a. Block size / cache line = 2 offset bits = 2 4 bytes= 16 bytes…

Answered: [15] For a direct mapped cache design…

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 22VE

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