1. Test the circuit above (use your own input values) and note down the sequence of outputs in Table 11.1 after each successive clock pulse and obtain the timing diagram.

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Shift Register Operations
4-bit Parallel Data Output
Qa
QB
Qc
QD
Serial
FFA
FFB
FFC
FFD
Serial
Data out
Data in
CLK
CLK
CLK
CLK
CLR
CLR
CLR
CLR
Clear
Clock
Figure 11.1: Serial input shift register (SISO+SIPO)
1. Test the circuit above (use your own input values) and note down the sequence of outputs in
Table 11.1 after each successive clock pulse and obtain the timing diagram.
Table 11.1: Truth Table for Shift Register
COUNT
QA
Q8
Qc
Qo
1
4
6.
7
8
Transcribed Image Text:Shift Register Operations 4-bit Parallel Data Output Qa QB Qc QD Serial FFA FFB FFC FFD Serial Data out Data in CLK CLK CLK CLK CLR CLR CLR CLR Clear Clock Figure 11.1: Serial input shift register (SISO+SIPO) 1. Test the circuit above (use your own input values) and note down the sequence of outputs in Table 11.1 after each successive clock pulse and obtain the timing diagram. Table 11.1: Truth Table for Shift Register COUNT QA Q8 Qc Qo 1 4 6. 7 8
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