1. Flip-flops have both synchronous and asynchronous inputs. Describe each input type and give an example of each.
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- Digital logic design Solve it with drawing and simulation lab I need them both to have the full solution. And thanks Design counter that counts from 00 to 59, using the IC 74LS90 ripple counter and use two 7 segment display to display the result count. You can also use 7447 binary to 7-segment Display Decoder.show the waveforms for each flip-flop output with respect For the ring counter in Figure to the clock. Assume that FF0 is initially SET and that the rest are RESET. Show at least ten clock pulses. D D. FFO FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 FP9 CLKT: Answer thne f. questions: 1) The hexadecimal number ´Al' has the decimal value equivalent to (A) 80 (B) 161 (C) 100 (D) 101 2) The output of a logic gate is 0 when all its inputs are logic 1. The logic is either (A) a NAND or an EX-OR (B) an OR or an EX-NOR (C) an AND or an EX-OR (D) an NOR or an EX-NOR 3) The Gray code of the Binary number 1100111 is (A) 1011011 (B) 1010100 (C) 1001001 (D) 101101 4) When simplified with Boollean Algebra (a+b)(a+c) simplifies to (A) a (B) a+a(b+c) (C) a(1+bc) (D) a+bc 5) -31 is represented as a sign Binary number ( using Sign-magnitude form ) equal to (A) 00011111 (B) 10101001 (C) 01110010 (D) 00101101 6) The Binary number 110111 is equivalent to decimal number (A) 25 (B) 55 (C) 26 (D) 34 7) With 4 bit, what the range of decimal values if the number is 2's complement signed number. (A) -32 to +31 (B) -2 to +1 (C) -8 to +7 (D) None of these
- Design a 6-bit counter with control input using flip-flops. Every hour pulseIt should be a design that will increase or decrease by 4 when it arrives. Control input increment orwill determine the decrease. Increasing when control input is 0, decreasing when 1should be designed.Refer to figure 2, carefully, analyze the sequential circuit which contains 2X4 active low decoder decoder, two 2X1 Mux, and JK flip- flop then answer the following questions: what is the state of JK flip-flop if A=0,B=0 and C=1. "note * A: is the most significant bit. C: least significant bit in the state table. **its best for you to draw the state table". 2x1 De FI 2x4 DA Low acti B cnt CIK a. Complement b. Rest c. No change O d. SetProblem 02: Equivalent to NAND Gate Draw an equivalent circuit to a three-input NAND gate using ouly one-input and two-input logic gates. Prove that your circuit is equivalent to a threo-input NAND gate.
- Feedback shift register is such type of register, whenA. each flip-flop transfers its content to the next flip-flopB. each flip-flop transfers its content to the next flip-flop, when a clock pulse occursC. each flip-flop transfers its content to the next flip-flop, when a clock pulse occurs, but the next state of the first flip-flop(for MSD) is some function of the present state of other flip-flopsD. each flip-flop transfers its content to the next flip-flop, when a clock pulse occurs, but the next state of the first flip-flop(for LSD) is some function of the present state of other flip-flopsE. each flip-flop transfers its content to the next flip-flop, when a clock pulse occurs, but the next state of the last flip-flop(for LSD) is some function of the present state of other flip-flops14.) Using rising edge JK-Flipflops and Digital Logic Gates, build a 4-Stage Shift Register. I recommend labeling D0, Q0, Q1, etc. Based on the waveforms for the CLK (clock) and D0 input generate the waveforms for Q0, Q1, Q2, Q3. DO CLK QO Q1 Q2 Q3Design the following combinational logic circuit with a four-bit input and a three-bit output. The input represents two unsigned 2-bit numbers: A1 A0 and B1 B0. The output C2 C1.C0 is the result of the integer binary division A1 A0/B1 B0 rounded down to three bits. The 3-bit output has a 2-bit unsigned whole part C2 C1 and a fraction part CO. The weight of the fraction bit CO is 21. Note the quotient should be rounded down, i.e. the division 01/11 should give the outputs 00.0 (1/3 rounded down to 0) not 00.1 (1/3 rounded up to 0.5). A result of infinity should be represented as 11.1. A minimal logic implementation is not required. (Hint: start by producing a truth table of your design).
- Construct and explain the operation of the following ripple counters with positive edge triggered D Flip-flops. - 4 bit binary asynchronous UP counter- 4 bit binary asynchronous DOWN counter- Asynchronous BCD Counter- Asynchronous MOD-12 Counter- Ripple divide by 14 CounterA 4-bit binary up/down counter is in the binary state of zero. The next state in the DOWNmode is (a) 0001 (b) 1111 (c) 1000 (d) 1110a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate thecomplete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform.(Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.)(Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.)