1 Determine the logical effort g, and the parasitic capacitance p, of the following compound gates: Y = (AB + CD + E)' Y = (A + BCD + E)'

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ECE 4112HW Chap 9
1 Determine the logical effort g, and the parasitic capacitance p, of the following compound gates:
Y = (AB + CD + E)'
Y = (A + BCD + E)'
2 For each gate in problem 1, determine the optimum sizes for the transistor for the minimum delay if
the gates are driving a 100C load.
3 Determine g and p for a 5-input NOR gate that favors one input.
4 Sketch HI-skew and LO-skew 4-input NAND and NOR gates. What are the logical
efforts of each gate on its critical transition?
5 Derive a formula for gu, gd, and gavg for HI-skew and LO-skew k-input NAND
gates with a skew factor of s <1 (i.e., the noncritical transistor is s times normal size)
as a function of s and k.
Consider circuits for the following gate Y = (AB + CD)'
Draw the transistor-level schematic in each of the technologies below including the transistor sizes for
optimal delay.
The parameters are: Cin = 10C, C̟ = 100C.
6 Static CMOS
7 Pseudo-NMOS
8 Domino (footed). Note that a Domino gate must be followed by an Inverter. Therefore, the nMOS
transistors will form a (AB + CD)' network, not an AB + CD as with the other two gates.
9 Repeat the designs with the three technologies above for the gate Y = (AB + CD)
Transcribed Image Text:ECE 4112HW Chap 9 1 Determine the logical effort g, and the parasitic capacitance p, of the following compound gates: Y = (AB + CD + E)' Y = (A + BCD + E)' 2 For each gate in problem 1, determine the optimum sizes for the transistor for the minimum delay if the gates are driving a 100C load. 3 Determine g and p for a 5-input NOR gate that favors one input. 4 Sketch HI-skew and LO-skew 4-input NAND and NOR gates. What are the logical efforts of each gate on its critical transition? 5 Derive a formula for gu, gd, and gavg for HI-skew and LO-skew k-input NAND gates with a skew factor of s <1 (i.e., the noncritical transistor is s times normal size) as a function of s and k. Consider circuits for the following gate Y = (AB + CD)' Draw the transistor-level schematic in each of the technologies below including the transistor sizes for optimal delay. The parameters are: Cin = 10C, C̟ = 100C. 6 Static CMOS 7 Pseudo-NMOS 8 Domino (footed). Note that a Domino gate must be followed by an Inverter. Therefore, the nMOS transistors will form a (AB + CD)' network, not an AB + CD as with the other two gates. 9 Repeat the designs with the three technologies above for the gate Y = (AB + CD)
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