. Modify your D flip flop again to produce a 1-bit register with extra inputs rst, shift, D, and Do. Do is an initial condition (0 or 1) that is applied when rst is HIGH. The D flip flop has the following functions: Function Name Reset Shift Hold Signal rst shift shift Operation when rst == 1, Q = Do when rst == 0 and shift == 1, Q = D when rst == 0 and shift == 0, Q = Q D clk Q Q'

. Modify your D flip flop again to produce a 1-bit register with extra inputs rst, shift, D, and Do. Do is an initial condition (0 or 1) that is applied when rst is HIGH. The D flip flop has the following functions: Function Name Reset Shift Hold Signal rst shift shift Operation when rst == 1, Q = Do when rst == 0 and shift == 1, Q = D when rst == 0 and shift == 0, Q = Q D clk Q Q'

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Create a circuit using Logism that implements a memory register capable of storing a 4-bit binary number. You should investigate the different circuits that can be used to store a bit of memory and then utilize the one that meets the following requirements. Your register circuit must be able to support the inputs detailed in the ATTACHED diagram. Each bit of the register circuit must support a data in, a data out, and a control. The control functions such that the data value will only be changed when the control bit is toggled on. The value in the register must be persistent and can only be changed when the control bit has been toggled. You should develop and test the 4-bit register using logism. When you have successfully developed a functioning 4-bit register, you should duplicate the circuit and add it to the two inputs of the ALU circuit that you developed in the previous unit. Complete and test all of your circuits using Logism.
Given the schematic: Replace the five D Flip-Flops with an 8-bit shift register (SR8 from the ISE symbols set). Use a 4-input XNOR, feedback Q4, Q5, Q6 and Q8, where Q1 is the leftmost register and after each clock, the shift is from left to right; that is from Q1 to Q2; Q2 to Q3; etc. Replace the 2-input XNOR with a 2-input XOR. REMINDER: The trick is to make sure you initial the 5-bit binary value to non zero on only the first clock pulse.
The following circuit is a pseudo-random number generator which uses linear feedback shift registers to produce a stream of outputs. The XOR tap at index ‘1’ is responsible for generating this sequence of outputs. Fill in the table for the outputs of the 4 registers after each clock cycle. The initial output state is already provided in the first row. You can stop when the output starts to repeat and just say that it is repeating. For a 3-bit LFSR with similar implementation as above, what ‘index’ should the NOR tap be placed at in order to generate the following sequence of outputs for (Q2, Q1, Q0); 000, 100, 001, 110, 001, 110 (Note that there is only one NOR tap in this circuit.
Given the schematic: Replace the five D Flip-Flops with an 8-bit shift register (SR8 from the ISE symbols set). Use a 4-input XNOR, feedback Q4, Q5, Q6 and Q8, where Q1 is the leftmost register and after each clock, the shift is from left to right; that is from Q1 to Q2; Q2 to Q3; etc. Replace the 2-input XNOR with a 2-input XOR. The trick is to make sure you initial the 5-bit binary value to non zero on only the first clock pulse.
Your task is to write code to implement a two-tone siren using the QUTy. You must use one of the Waveform Outputs of TCA0 to drive the buzzer. The buzzer should always be driven with a 50% duty cycle signal. Your siren must alternate between the following frequencies: f1 = 2110 Hz with f1 active for t1 = 370 ms f2 = 4960 Hz with f2 active for t2 = 630 ms NOTE: Your programme must be interrupt driven. dc = 50% main() will call the init() function you write below and then drop into an infinite loop. The init() function you write MUST return to demonstrate your code is interrupt driven. In addition to init(), you may write any code you wish in this file, including ISRs. // NOTe: make sure to use the buffered versions of the CMP/PER registers //! NOTE: DO not use _delay_ms or _delay_us, we want you to do the math //! yourself and make your program interrupt driven in this program the buzzer should play f1 hz for t1 time, then play f2 hz t2 time, and it's play again and…
If you only had 4:16 One Hot Decoder and an OR gate with the number of inputs of your choosing, fill in the blanks to explain how you would implement the function !x3x2 + x2x0 + !x3!x1x0 with the hardware you were provided. There are 4 inputs for this function, x3-x0. 1. How many inputs an OR gate would connect to? 2. For input x3,x2,x1,x0, I would connect it input to which options: (0, 1, 2,3) of the decoder. 3. Which outputs of the decoder will not use to connect to the OR gate.
Write down a register transfer statement of 'contents of R1 minus R2 transferred to R3' for a system which has only an adder, but not a subtractor.
Use EDAplayground.com for parts A and B A). Design 3-bit rollback up/down counter. Make sure to include a control signal called “count-direction” in your design. If count-direction = 1, your counter should be incremented by 1 per each clock cycle. If count-direction = 0, your counter should be decremented by 1 per each clock cycle. Since it is a rollback counter, your count should rollback from 111 to 000 when counting up or 000 to 111 when counting down. B) Create a testbench to test your DUV. You need to use count-direction = 0 for 16 clock cycles. Then, use count-direction = 1 for 16 clock cycles. Make sure to limit your simulation run time to allow simulation data for 32 clock cycles is collected to draw a timing waveform.
Using D-flip flops, design a 4-bit shift register with parallel load and two control inputs shift andload. The criteria is such that when shift = 1 the contents of the register is shifted by oneposition. New data are transferred into the register when load = 1 andshift = 0. If both inputs are zero, the contents of the register should not change.a. Create a function table for the shift registerb. Design for the next state equation for the D-flip-flops.c. Draw the logic diagram for the ith stage of the 4-bit register
Write a VHDL program which uses the following Must use LPM Shift Register Input lables must be following, CLK for clock, S_IN for Serial Input, P_OUT for parallel output. P_OUT width should be 6-Bit Shift Register Direction "LEFT
consider what you would do for A, B, and C individually. Refer to the D latch diagram. For the given clock and D signals, what is the resulting output at Q? For the D register, using the same clock and D signals, what is the resulting outputs at -QL and QR? You can use the dashed boxes shown under the given signals for your answers, though you should provide a written explanation, too.
Using Logism Softwarel The most important and possible most difficult component to implement is the 8 bit arithmetic logic unit. Thefunctions of the ALU are shown in Table 1. The ALU should have 5 inputs (A-input, B-input, F0-input, F1-input, Finput) and 1 output (C-output). You will need to determine how many bits each input and output should have.Remember, you are designing an 8-bit microprocessor! . For example, to add the value on the A-bus8-bit ALUto the value on the B-bus, you can simply use an 8-bit adder. Explore the components in Logisim! Additionally,you can think about using a multiplexer to determine which ALU function will be performed