. Implement a Full Adder and Full Subtractor using (a) HAs (for FA) / HSs (for FS) and appropriate gates (b) Decoders (c) MUXs ** give/ show the basis for your designs
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2. Implement a Full Adder and Full Subtractor using
(a) HAs (for FA) / HSs (for FS) and appropriate gates (b) Decoders (c) MUXs
** give/ show the basis for your designs
Step by step
Solved in 4 steps with 3 images
- Logic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions. Task 2: 4 INPUT PRIORITY ENCODERa) Write the truth table.b) Find the outputs in terms of min terms using minimal expression.c) By using K map, find the simple/simplest expression of theoutputs.d) Draw the circuit diagram. (Simulation design will be accepted.)e) Simulate the circuit & explain your results. (Please do notdesign separate simulations for each output. You should design ONEsimulation including all inputs and outputs.)Logic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions.Task 1: 2-to-1 LINE MULTIPLEXER DESIGNA) Write the truth table of 2-to-1 line multiplexer.B) Draw the circuit diagram by using only NAND & NOT GATES.C) Simulate the circuit that you found in part B.The only function of a not gate is to …..A. stop a signalB. re-complement a signalC. invert an output signalD. act as a universal gate
- d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.Q1: First develop the Boolean expression for the output of each gates network and simplify. 1. BJOIN 3 circuits below(1,2 and 3) in a carry-ripple adder configuration and demonstrate binary addition of two three-bit numbers using a minimum of four number pairs that include both negative and positive numbers (signed 2s complement representation) and at least one overflow result. Circuit 1: a full-adder using any combination of gates from the following ICs: 7400, 7404,7408, 7410, 7420, 7432, and 7486 Circuit 2: a full-adder using a single 74138 IC and any additional assorted gates that may be necessary Circuit 3: a full-adder using a single 74138 IC and assorted gates.
- parity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.1E. Write a VHDL code for all Logic Gates and verify Output waveforms. 2E. Write a VHDL code for Half Adder and verify Output waveforms. 3E. Write a VHDL code for Full Adder and verify Output waveforms.Assume that the exclusive-OR gate has a contamination delay of 10 ns and that the AND or OR gates have a contamination delay of 5 ns. What is the total contamination delay time in the 8-bit adder? Note: your answer should include only the value of the delay without the unit (only the number) A B- Cin- Cout Answer:
- The numbers from 0-9 and a no characters is the Basic 1 digit seven segment display * .can show False True In a (CA) method of 7 segments, the anodes of all the LED segments are * "connected to the logic "O False True Some times may run out of pins on your Arduino board and need to not extend it * .with shift registers True FalseQ (A, B, C) = A̅ .B̅. C +A̅ .B. C + A .B. C̅ + A.B.C. Obtain the simplified function with the Karnaugh Map method in terms of minterms and maxters separately. Set the output functions separately with logic gates with AND NOT for minterms and OR for maxima.(b) For a gated S-R latch. determine the Q output for the inputs in the following Figure. Show it in proper relation to the enable input, also draw the input waveforms on your answer script. Assume that Q starts LOW. EN S R Minimize the combinational logic circuit in the following figure using Karnaugh's map only. Inverters for the complemented variables are not shown. Q2.