REPORT 2

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University of Toledo *

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3400

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Electrical Engineering

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Dec 6, 2023

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1 Lab Report Experiment 2 Op Amps - A Basic Analog Building Block EECS 3400 Electronics Lab I by Simran Shekhar with Ananya Singh 09/19/2023

2 Introduction The objective of this experiment is to investigate a variety of fundamental operational amplifier (Op Amp) circuits. We will employ the widely recognized '741 Op Amp in conjunction with either one or two 15V power sources. Operational amplifiers, commonly referred to as Op Amps, are fundamental components in the world of electronics and electrical engineering. These versatile integrated circuits have a remarkable ability to amplify, condition, and manipulate analog signals, making them an essential building block for a wide range of electronic applications. Materials Required This experiment necessitates the utilization of a function generator and an oscilloscope that possesses dual-trace and X-Y functionality. We will employ the web-based interface of the oscilloscope to capture waveform data and generate X-Y plots, which will be incorporated into the laboratory report Pre-Lab No pre-lab was required. However, it can be seen that it would always be handy to use the web browser to DSO connection should it be necessary to record some experimental waveforms. Procedure The “Protoboard” was first obtain. The lab group proceeded to obtain the capacitors, OP-AMP IC, and resistors, wiring them together as shown in the following circuit diagrams from the lab handout respectively:

3 Circuit I. Inverting Amplifier Circuit II. Non-inverting Amplifier Circuit III. Integrator with dc stabilization

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4 Theory Both “inverting” and “non - inverting” configurations of an OP -AMP receive feedback from the output of the amplifier at the inverting input (negative input t erminal, pin 2 of the ‘741). The distinction between the these configurations is that for the “inverting” configuration, the input is applied at the inverting input terminal, while for “non - inverting” configuration, the input is applied at the non - invertin g input (positive input terminal, pin 3 of the ‘741). Fig 0. Vin is applied to pin 2 for inverting configurations, 3 for non- inverting for the ‘741. An ideal OP-AMP has infinite voltage gain, infinite input impedance, zero output impedance, and gain that is independent of frequency. The ideal gain of an inverting amplifier is given by G = − R 2 . R 1 The ideal gain of the inverting amplifier of Fig. 1 of the lab handout therefore can be theoretically calculated as G 100. An OP- AMP’s output voltage signal cannot be higher than the positive power supply voltage, and no lower than the negative power supply voltage. Clipping thus will occur when V out , the value of the input signal voltage (Vin) multiplied by the gain (A), exceeds either of the said boundaries [1]. The image below in Fig. 1 demonstrates clipping.

5 Fig 1. Output C1 is clipped and inverted relative to Input signal C2. The maximum allowable output signal level in Fig.1 of the lab handout is, therefore, +15 V on the upper-bound, -15V on the lower bound, and the saturation levels of V out of the circuit is determined by two 15V power supplies. The gain of the circuit in Fig. 1 of the lab handout when measured should be frequency dependent because the constructed circuit will not be an ideal OP-AMP, and frequency dependence is a characteristic of ideal OP-AMPs. The ideal gain of a non-inverting amplifier is given by G = 1 + R 2 . The ideal of gain of the R 1 non- inverting amplifier shown in Fig. 2 of the lab handout can be theoretically calculated as 100 10 3 G . The image in Fig. 2 shows a non-inverting OP- AMP’s input and output signals for a gain of approximately 11.

6 Fig. 2. Input signal C2 is amplified by a non-inverting OP-AMP to produce output signal C1. − 1 t The integrator OP-AMP output signal is defined as V out = R 1 Cf ∫ Vin 0 dt for an ideal integrator. The OP-AMP integrating circuit output voltage is proportional to the area under the input waveform (the integral of the waveform). When the input voltage is 0V, there should theoretically be no current through the input resistor R1 and the capacitor will be uncharged. Resistor R2 in Fig 3. prevents saturation of the output voltage. Saturation happen C sw d h v en the feedback capacitor behaves like an open circuit as the input frequency is 0 Hz (where i = = 0 ), and thus the integrator circuit behaves c dt like an inverting [2]. If R2 were omitted, the integrator’s transfer function would practically behave as an ideal integrator, where the transfer function is Vout . Fig. 3, shown below, R 1 Cf 0 demonstrates the relationship between an input and output signal in an integrator circuit.

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7 Fig. 3. Output signal C1 is the inverse of the time integral of square wave input signal, C2, due to the integrator OP-AMP. Discussion The Inverting amplifier was programmed to output an inverted sine wave. The function generator was set to produce a 1-kHz 100-mV p-p sine wave with zero dc offset and applied to Vin. With probe 2 set as the input and probe 1 as the output, we recorded the resulting waveforms. The input and output waveforms are shown inverted to each other (See Fig. 4). Fig. 4. Inverting Waveforms With an inverting amplifier Vgain = R2/R1. Looking at Figure 1

8 (See Fig. 1), we get: 1 × 10 6 G = 4 = 100 . We then went on to calculate the voltage gain from the waveforms given, defined 1 × 10 as: v out G = v ¿ For 1-kHz, V out = 10.86V and Vin was equal to 107.8mV. Using these values, we were able to calculate the gain: 10.86 G = = 99.07 .1078 99.07 is within 1% of the predicted gain of 100 showing our waveforms are correct. We then to find measurements of the voltage gain at the following frequencies: 100 Hz, 1 kHz, and 10 kHz. The calculations for this are as follows: Vout Vin Voltage Gain 10.83 V 107.8 mV 100.46 10.68 V 107.8 mV 99.07 6.32 V 107.3 mV 59.90 The output signal level saturates at an output voltage near the negative voltage source, in this case -15V. When looking at the results from the three frequency inputs you see that the measured gain is frequency dependent. The maximum output is in a distinct band of frequencies. If the frequency is below or above the bandwidth, the output will decrease respectively. Looking at the gain with when using a 10 kHz frequency, we see that this frequency is in the higher corner causing the gain to decrease. Increasing the 100-Hz input Vin gradually eventually caused distinct clipping at both peaks of the output waveform. We then recorded the two

9 waveforms and the X-Y mode. On the vertical axis is Vout and Vin is on the horizontal. We then changed the dc power supplies to +5V and -15V and the function generator for a 100-Hz 100-mV p-p sine wave with zero dc offset. We again gradually increased the amplitude and observed the output waveform until there was distinct clipping at both peaks. We then recorded the resulting X-Y plot of Vout vs. Vin. (See Fig. 6) The non-inverting amplifier was programmed to produce a sine wave. We set the function generator to produce a 1-kHz 1-V p-p sine wave with zero dc offset. We measured the peak-to-peak values of both waveforms representing the input and output. Like an inverting amplifier, gain is calculated by: G = Vout / v ¿ To check your measurements, we used to formula for voltage gain for a non- inverting amplifier: G=1+(R 1 ) To calculate the voltage gain we need Vout and Vin. We got Vout from C1. Vout = 11.6. Vin is from C2. Vin = 1.06. 11.6 G = = 10.94 1.06 The measured gain is within 1% of the calculated gain. We constructed the integrator amplifier circuit with both positive and negative 15-V power supplies. We added a dc stabilization resistor in parallel with a 0.1μF paper - dielectric capacitor. The function generator was set to produce a 1-kHz 20-V p- p square wave with zero dc offset. The input waveform was a square wave, but the output became a sawtooth wave. (See Fig. 7) When shorting the two input terminals we observed the output voltage and measured 0.032V. The measured voltage was close to zero but not exactly due to the remaining charge left in the capacitor parallel to R2. We then pulled the dc stabilization resistor R2. The output voltage then began to increase and became saturated at around 14.4V.

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10 With R2 out of the circuit, the capacitor was no longer in parallel with a resistor so there was no longer resistance in that loop. If R2 were omitted, the integrator’s transfer function would practically behave as an ideal integrator, where the transfer function is t − 1 Vou of t = ∫ Vin d . The output voltage is not zero when the input signal is zero because R 1 Cf 0 the initial voltage constant term of the V out integral when evaluat Conclusion: In this way we can explore operational amplifier circuits and their different modes, which are inverting, non-inverting, and integrator. All the questions asked in the lab guidelines have been answered in the above lab report.

11 Report Your report should address the following: 1. Predict the ideal voltage gains of Figs. 1 and 2, based on an infinite-gain OP-AMP. 2. What is the distinction between the "inverting" and "non-inverting" configurations? 3. Discuss the maximum allowable output signal level in Fig. 1. What determines the saturation levels of Vout? 4. Why is the measured gain of Fig. 1 frequency dependent? 5. Predict the ideal transfer function of Fig. 3 if R2 were omitted. 6. Why is the integrator output voltage not zero with zero input signal? 7. What happens when R2 is pulled? Why? 1. Predict the ideal voltage gains of Figs. 1 and 2, based on an infinite-gain OP-AMP: • For the inverting amplifier (Fig. 1), the ideal voltage gain can be calculated using the formula: Gain = -Rf / Rin, where Rf is the feedback resistor and Rin is the input resistor. In an ideal scenario with an infinite-gain Op-Amp, the voltage gain would also be infinite. • For the non-inverting amplifier (Fig. 2), the ideal voltage gain can be calculated as: Gain = 1 + (Rf / Rin), where Rf is the feedback resistor and Rin is the input resistor. With an infinite-gain Op-Amp, the voltage gain would be equal to the ratio of the feedback resistor to the input resistor. 2. What is the distinction between the "inverting" and "non-inverting" configurations: • The primary distinction between the inverting and non-inverting configurations is in how they amplify the input signal: • In the inverting configuration, the output is the inverted (180- degree phase shift) version of the input signal. The voltage gain can be greater than or less than 1 depending on the ratio of the feedback resistor to the input resistor. • In the non-inverting configuration, the output is in phase with the input signal. The voltage gain is always greater than or equal to 1 and can be easily adjusted using the feedback resistor. 3. Discuss the maximum allowable output signal level in Fig. 1. What

12 determines the saturation levels of Vout: • The maximum allowable output signal level in Fig. 1 is limited by the power supply voltage. In experiment, when using +15V and -15V supplies, the maximum output signal level would be approximately ±15V. This is because an ideal Op-Amp cannot output a voltage beyond the range of its power supply. 4. Why is the measured gain of Fig. 1 frequency dependent? • The measured gain of the inverting amplifier (Fig. 1) is frequency- dependent due to the Op-Amp's limited bandwidth. Op-Amps have a finite bandwidth, and their gain decreases as the frequency of the input signal increases. This phenomenon is often described by the Op-Amp's open-loop gain and the unity-gain bandwidth. As the frequency increases, the gain decreases, resulting in a frequency-dependent response. 5. Predict the ideal transfer function of Fig. 3 if R2 were omitted: • If R2 were omitted in the integrator circuit (Fig. 3), the ideal transfer function would be a simple integration of the input signal. The output voltage (Vout) would be proportional to the integral of the input voltage (Vin) with respect to time. The ideal transfer function can be expressed as Vout = - 1 / (R1 * C1) ∫Vin dt, where R1 is the resistor and C1 is the capacitor used in the circuit. 6. Why is the integrator output voltage not zero with zero input signal: • The integrator output voltage is not zero with zero input signal due to the presence of bias currents and input offset voltage in the Op-Amp. In practical Op-Amps, there are small input offset voltages and bias currents that can cause a DC (direct current) component in the output. These imperfections result in a non-zero output voltage even when the input is zero. 7. What happens when R2 is pulled? Why: • When If R2 is removed from the integrator circuit (Fig. 3), the circuit will behave as a straightforward integrator, provided that there's a ground connection at the junction of the capacitor (C3) and the resistor (R1). In the absence of R2, the circuit simplifies to a basic integrator configuration with a transfer function: Vout = - 1 / (R1 * C1) ∫Vin dt In this configuration, the circuit integrates the input voltage signal over time. This is because R2 typically serves as a resistor for DC biasing and stability in the circuit. However, when removed, the circuit becomes a standard integrato

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