Q) Design an architecture using a RISC processor instruction set that is capable of reading two numbers (a and b) from memory addressed at 0000h and 0OFFh and calculate the function c = a-b+ 3 and return the results to pre-assumed memory location. Write code segment to implement the function.
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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?1. Write RISC-V assembly language to implement the common function c = max(a,b) which assigns to c the value of a or b which is larger. You can choose either registers or memory locations to assist the action. Briefly describe the problem. Provide two screenshots: One before program run with initialized register values or memory values. One after program run with register or memory location values. Attach assembly code and explain two lines of machine codes from your program in binary level.2. An implementation of the above RISC-V microprocessor has been designed where the supported instructions are classified as follows with regard to the number of cycles required to execute: Arithmetic & Logic: 4 cycles Memory Access: 5 cycles 3 cycles Branching: System Calls: 1 cycle What is the average CPI for this microprocessor? (includes lui, add, addi, or, ori, sub, and, (includes all loads and stores) (includes blt, beq, bne) (includes ecall) andi)
- Write RISC-V assembly language to implement the common function c = max (a, b) which assigns to c the value of a or b which is larger. You can choose either registers or memory locations to assist the action.As part of the von Neumann architecture, the a) processing unit and b) programmer counter serve which of the following?Determine the value in LR (R14) and PC (R15) when microprocessor is executing theinstruction in Line 21 (SUBS R0, R0, #0x05).
- Translate the following user-level instruction to a microprogram so it can be directly executed by the vertical architecture (VA) attached. 1.b Also show the opcode and register representation in hexadecimal for each finding VA instruction. B := D – BAND(C+D) if B < 0 GOTO 70;Q: The ENIAC was a decimal machine, where a register was represented by a ring of 10 vacuum tubes. At any time, only one vacuum tube was in the ON state, representing one of the 10 digits. Assuming that ENIAC had the capability to have multiple vacuum tubes in the ON and OFF state simultaneously, Compare how Little’s and Amdahl’s law will work on it? Note: this question is related from computer architecture subject kindly solved this correctly and completly.8, Provide the type, assembly language instruction, and binary representation of instruction described by the following MIPS fields: op = 0, rs = 16, rt= 15, rd = 25, shamt = 0, function = 34
- TRUE OR FALSEMost architectures today are accumulator based.Q1. Write microcode for the execution part of the following CISC instruction. Give both a register transfer description and binary or hexadecimal representations. Add with carry: R[DR] + R[SA]+R[SB]+c Action Address MZ CA RW DX MD BS PS FS LC MA MB AX BX CS4) Write an ALP for 8086 microprocessor to solve the following equation Y = (A x B) + C. A, B and C are 8 bit input variables in HEX. Note: Please do not handwritten.