Computer Systems: A Programmer's Perspective (3rd Edition)
3rd Edition
ISBN: 9780134092669
Author: Bryant, Randal E. Bryant, David R. O'Hallaron, David R., Randal E.; O'Hallaron, Bryant/O'hallaron
Publisher: PEARSON
expand_more
expand_more
format_list_bulleted
Question
Chapter 3.5, Problem 3.11PP
a.
Program Plan Intro
Logical Instructions:
- The instructions provided by processor includes:
- AND:
- It performs bitwise “AND” operation.
- It returns 1, if matching bits from both operands are 1.
- OR:
- It performs bitwise “OR” operation.
- It returns 1, if matching bits from either or both operands are 1.
- XOR:
- It performs bitwise “XOR” operation.
- It sets bit to 1, if bits from operands are different.
- NOT:
- It performs bitwise “NOT” operation.
- It reverses bits in an operand.
- AND:
- The “orq” instruction performs bitwise “OR” operation on 8 bytes data size.
- The “notq” instruction performs bitwise “NOT” operation on 8 bytes data size.
b.
Program Plan Intro
Data movement instructions:
- The different instructions are been grouped as “instruction classes”.
- The instructions in a class performs same operation but with different sizes of operand.
- The “Mov” class denotes data movement instructions that copy data from a source location to a destination.
- The class has 4 instructions that includes:
- movb:
- It copies data from a source location to a destination.
- It denotes an instruction that operates on 1 byte data size.
- movw:
- It copies data from a source location to a destination.
- It denotes an instruction that operates on 2 bytes data size.
- movl:
- It copies data from a source location to a destination.
- It denotes an instruction that operates on 4 bytes data size.
- movq:
- It copies data from a source location to a destination.
- It denotes an instruction that operates on 8 bytes data size.
- movb:
- The “subq” instruction decrements the second operand by value in first operand.
c.
Program Plan Intro
Data movement instructions:
- The different instructions are been grouped as “instruction classes”.
- The instructions in a class performs same operation but with different sizes of operand.
- The “Mov” class denotes data movement instructions that copy data from a source location to a destination.
- The class has 4 instructions that includes:
- movb:
- It copies data from a source location to a destination.
- It denotes an instruction that operates on 1 byte data size.
- movw:
- It copies data from a source location to a destination.
- It denotes an instruction that operates on 2 bytes data size.
- movl:
- It copies data from a source location to a destination.
- It denotes an instruction that operates on 4 bytes data size.
- movq:
- It copies data from a source location to a destination.
- It denotes an instruction that operates on 8 bytes data size.
- movb:
- The “subq” instruction decrements the second operand by value in first operand.
Logical Instructions:
- The instructions provided by processor includes:
- AND
- It performs bitwise “AND” operation.
- It returns 1, if matching bits from both operands are 1.
- OR
- It performs bitwise “OR” operation.
- It returns 1, if matching bits from either or both operands are 1.
- XOR
- It performs bitwise “XOR” operation.
- It sets bit to 1, if bits from operands are different.
- NOT
- It performs bitwise “NOT” operation.
- It reverses bits in an operand.
- AND
- The “orq” instruction performs bitwise “OR” operation on 8 bytes data size.
- The “notq” instruction performs bitwise “NOT” operation on 8 bytes data size.
Expert Solution & Answer
Want to see the full answer?
Check out a sample textbook solution
Students have asked these similar questions
(c) The following Sigma 16 program has been loaded into memory at address 0000:
load R3,y[RO]
load R4,x[RO]
lea R5, 2[RO]
sub R1,R4,R3
mul R2,R1,R5
store R2,w[RO]
trap RO,RO,RO
x data 10
y data 12
w data 0
Show the content of the memory writing hexadecimal representation and using a
table with 3 columns: the memory address, the contents of that memory address,
and an explanation of what "the content (of that memory address) means". As a
reference, here are the opcodes for RRR instructions: add 0, sub 1, mul 2, trap c.
And here the opcodes for RX instructions: lea 0, load 1, store 2.
[7]
(b) (i)
(ii)
Elaborate how we can identify the instruction format (i.e., R-, I- or J-
type) of a machine code.
Translate the following machine code to MIPS assembly code. Show
all your workings.
0x0125882A
(e) Instruction(s) to copy contents at one memory location to another: C[g] =A[i+j-3). Assume i, j,g values are in registers x5, x6, x7. Assume base address in memory of Array data structures 'A, B' (or address in memory of 'A[O]' and 'B[O]') are stored in Registers x28, 29• In RISCV, only load and store instructions access memory locations • These instructions must follow a 'format' to access memory • Assume a 32 bit machine in all problems unless asked to assume otherwise
Chapter 3 Solutions
Computer Systems: A Programmer's Perspective (3rd Edition)
Ch. 3.4 - Prob. 3.1PPCh. 3.4 - Prob. 3.2PPCh. 3.4 - Prob. 3.3PPCh. 3.4 - Prob. 3.4PPCh. 3.4 - Prob. 3.5PPCh. 3.5 - Prob. 3.6PPCh. 3.5 - Prob. 3.7PPCh. 3.5 - Prob. 3.8PPCh. 3.5 - Prob. 3.9PPCh. 3.5 - Prob. 3.10PP
Ch. 3.5 - Prob. 3.11PPCh. 3.5 - Prob. 3.12PPCh. 3.6 - Prob. 3.13PPCh. 3.6 - Prob. 3.14PPCh. 3.6 - Prob. 3.15PPCh. 3.6 - Prob. 3.16PPCh. 3.6 - Practice Problem 3.17 (solution page 331) An...Ch. 3.6 - Practice Problem 3.18 (solution page 332) Starting...Ch. 3.6 - Prob. 3.19PPCh. 3.6 - Prob. 3.20PPCh. 3.6 - Prob. 3.21PPCh. 3.6 - Prob. 3.22PPCh. 3.6 - Prob. 3.23PPCh. 3.6 - Practice Problem 3.24 (solution page 335) For C...Ch. 3.6 - Prob. 3.25PPCh. 3.6 - Prob. 3.26PPCh. 3.6 - Practice Problem 3.27 (solution page 336) Write...Ch. 3.6 - Prob. 3.28PPCh. 3.6 - Prob. 3.29PPCh. 3.6 - Practice Problem 3.30 (solution page 338) In the C...Ch. 3.6 - Prob. 3.31PPCh. 3.7 - Prob. 3.32PPCh. 3.7 - Prob. 3.33PPCh. 3.7 - Prob. 3.34PPCh. 3.7 - Prob. 3.35PPCh. 3.8 - Prob. 3.36PPCh. 3.8 - Prob. 3.37PPCh. 3.8 - Prob. 3.38PPCh. 3.8 - Prob. 3.39PPCh. 3.8 - Prob. 3.40PPCh. 3.9 - Prob. 3.41PPCh. 3.9 - Prob. 3.42PPCh. 3.9 - Practice Problem 3.43 (solution page 344) Suppose...Ch. 3.9 - Prob. 3.44PPCh. 3.9 - Prob. 3.45PPCh. 3.10 - Prob. 3.46PPCh. 3.10 - Prob. 3.47PPCh. 3.10 - Prob. 3.48PPCh. 3.10 - Prob. 3.49PPCh. 3.11 - Practice Problem 3.50 (solution page 347) For the...Ch. 3.11 - Prob. 3.51PPCh. 3.11 - Prob. 3.52PPCh. 3.11 - Practice Problem 3.52 (solution page 348) For the...Ch. 3.11 - Practice Problem 3.54 (solution page 349) Function...Ch. 3.11 - Prob. 3.55PPCh. 3.11 - Prob. 3.56PPCh. 3.11 - Practice Problem 3.57 (solution page 350) Function...Ch. 3 - For a function with prototype long decoda2(long x,...Ch. 3 - The following code computes the 128-bit product of...Ch. 3 - Prob. 3.60HWCh. 3 - In Section 3.6.6, we examined the following code...Ch. 3 - The code that follows shows an example of...Ch. 3 - This problem will give you a chance to reverb...Ch. 3 - Consider the following source code, where R, S,...Ch. 3 - The following code transposes the elements of an M...Ch. 3 - Prob. 3.66HWCh. 3 - For this exercise, we will examine the code...Ch. 3 - Prob. 3.68HWCh. 3 - Prob. 3.69HWCh. 3 - Consider the following union declaration: This...Ch. 3 - Prob. 3.71HWCh. 3 - Prob. 3.72HWCh. 3 - Prob. 3.73HWCh. 3 - Prob. 3.74HWCh. 3 - Prob. 3.75HW
Knowledge Booster
Similar questions
- 2. [4pts] Use the following C-Code for the problems below. int recFunc (int a, int b) { if (b = 0) == return a; else return 1+recFunc (a, b-1); a. Give the flowchart for the C-Code b. Convert to MIPS assembly and comment each assembly instruction to indicate corresponding C-Code.arrow_forward1. A. Convert the following C code into AT&T assembly: x at 8(%ebp) if (x>5){ X++; } else { X--; } while (x<10){ x++; } B. Annotate each line of the assembly code to describe how it operates. C. Write a goto version of the function (in C) that mimics how the assembly code program operates.arrow_forwardProblem 1.10: Simplify F(A, B,C, D) = ACD+ A'B + D'arrow_forward
- (Base Indexed Memory Addressing Mode) Only at [{DS | sS | ES} : {SI | DI} + {BX + BP}] BA EA There is a combination between (Base and Index) in Effective Add. (EA) Ex. Described each line and write down the equation of physical add. For the following assembly code: 01 org 100 02 MOV [BX+DI], CL оз мOV CH, [BX+SI] 04 MOV AH, [BP+DI] 05 MOV [BP+SI], AL 06 ret Sol:arrow_forward4.25. Use the equations in the book or the computer program of this chapter. Find the radiation efficiency of resonant linear electric dipoles of length (a) I = 1./50 (b) I=1/4 (c)l=1/2 (d)1 =1 Assume that each dipole is made out of copper [o = 5.7 x 107 S/m], has a radius of 10-42, and is operating at f = 10 MHz. Use the computer program Dipole of this chapter to find the radiation resistances.arrow_forward(a) In a DLX machine, an educational version of RISC machines, conditional branch instructions are designed as the fixed length of 32 bits. Briefly describe the format of branch instructions in encoding, and indicate the possible problem introduced by branch instructions when the machine is pipelined.arrow_forward
- Problem #2: [35 pts] Parity Bit CheckerThe parity bit of a sequence of bits is 0 if the number of 1’s in the sequence is even and 1otherwise.Example: if the sequence of bits is 1 1 0 1, the parity bit should be 1 (total number of 1-bits is 3 whichis odd) if the sequence of bits is 1 0 1 0, the parity bit should be 0 (total number of 1-bits is 2 whichis even)Write a Java program that asks the user to enter the number of bits he has. The program thenreads the bits as separate integers. In the end, the program prints the parity bit on the screen. Ifthe use enters a bit value that is neither 0 nor 1, the entry should be discarded and a messagedisplayed as shown in the sample run.Sample run 1:How many bits do you have? 6Enter 6 bits: 1 1 0 0 1 0The parity bit is 1Sample run 2:How many bits do you have? 8Enter 8 bits: 1 1 1 0 0 0 0 1The parity bit is 0Sample run 3:How many bits do you have? 5Enter 5 bits: 1 1 3 0 1Incorrect bit value 3 is discarded.The parity bit is 1 java brogramarrow_forwardCourse: ((computer architecture)) Problem: Memory: Given a 16Kx4 ROM memory chip; 1. What is the size of this ROM in Bytes? 2. Assuming the need to have one Control pin, one VCC and one VSS, Draw the smallest (i.e. number of pins) DIP package required to package this chip showing all pins with proper naming and directions.arrow_forwardProblem I ( Assembler ) Provide the assembly implementation of the C - code below . Sub 10 is a function that subtract 10 from a given input x. Assumption : MyArray base address is store in register $S1. Feel free to use instruction li or si. li load an immediate value into a register . For instance, li $S4 5 will copy value 5 into register $S4. C code for ( i = 0,1 < 10 , i ++ ) { MyArray [ i ] = MyArray [ i - 1 ] + MyArray [ i + 1 ] ; Sub10 ( MyArray [ i ]; } Sub10 ( x ) { Return ( x - 10 ) ; } Code in Assembly Language: sub10(int): ; Implementation of the sub10() function push rbp mov rbp, rsp mov DWORD PTR [rbp-4], edi mov eax, DWORD PTR [rbp-4] sub eax, 10 pop rbp ret main: ; Main function Implementation push rbp mov rbp, rsp sub rsp, 64 mov…arrow_forward
- Problem I ( Assembler ) Provide the assembly implementation of the C - code below . Sub 10 is a function that subtract 10 from a given input x. Assumption : MyArray base address is store in register $S1. Feel free to use instruction li or si. li load an immediate value into a register . For instance, li $S4 5 will copy value 5 into register $S4. C code for ( i = 0,1 < 10 , i ++ ) { MyArray [ i ] = MyArray [ i - 1 ] + MyArray [ i + 1 ] ; Sub10 ( MyArray [ i ]; } Sub10 ( x ) { Return ( x - 10 ) ; }arrow_forwardII LnecLIve Aud. (LA) Ex. Described each line and write down the equation of physical add. For the following assembly code: 01 org 100 02 MOV [BX+DI], CL 03 MOV CH, [BX+SI] 04 MOV AH, [BP+DI] 05 MOV [BP+SI], AL 06 ret Sol:arrow_forwardc. (3 Pts) In a certain computer architecture, the content of some registers and memory content currently is as follows. Memory Address Data R1 | 00000004 0000FFFE FO00128A R2 0000FFFE FO00128A 0000FFF0 Next, this computer execute the following instruction. ADDI (0000FFFE), R1 Note: The I in ADDI refers to Indirect. Indirect here deals with the destination address: (0000FFFE). The parentheses are standard for indirect addressing. ADDI means add content of source to content of destination and place result in destination. Given that it is immediately after the instruction above is executed, fill out the contents of registers and memory addresses below. Memory Address Data R1 0000FFFE R2 FO00128Aarrow_forward
arrow_back_ios
SEE MORE QUESTIONS
arrow_forward_ios
Recommended textbooks for you
Database System ConceptsComputer ScienceISBN:9780078022159Author:Abraham Silberschatz Professor, Henry F. Korth, S. SudarshanPublisher:McGraw-Hill Education
Starting Out with Python (4th Edition)Computer ScienceISBN:9780134444321Author:Tony GaddisPublisher:PEARSON
Digital Fundamentals (11th Edition)Computer ScienceISBN:9780132737968Author:Thomas L. FloydPublisher:PEARSON
C How to Program (8th Edition)Computer ScienceISBN:9780133976892Author:Paul J. Deitel, Harvey DeitelPublisher:PEARSON
Database Systems: Design, Implementation, & Manag...Computer ScienceISBN:9781337627900Author:Carlos Coronel, Steven MorrisPublisher:Cengage Learning
Programmable Logic ControllersComputer ScienceISBN:9780073373843Author:Frank D. PetruzellaPublisher:McGraw-Hill Education
Database System Concepts
Computer Science
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:McGraw-Hill Education
Starting Out with Python (4th Edition)
Computer Science
ISBN:9780134444321
Author:Tony Gaddis
Publisher:PEARSON
Digital Fundamentals (11th Edition)
Computer Science
ISBN:9780132737968
Author:Thomas L. Floyd
Publisher:PEARSON
C How to Program (8th Edition)
Computer Science
ISBN:9780133976892
Author:Paul J. Deitel, Harvey Deitel
Publisher:PEARSON
Database Systems: Design, Implementation, & Manag...
Computer Science
ISBN:9781337627900
Author:Carlos Coronel, Steven Morris
Publisher:Cengage Learning
Programmable Logic Controllers
Computer Science
ISBN:9780073373843
Author:Frank D. Petruzella
Publisher:McGraw-Hill Education