Write the VHDL code for the circuit shown in figure2. The circuit acts as support circuit for the control unit. It takes 5 bit from a 7 bit bus and start counting down at the rising Bus edge of each clock cycle in case the "Decr" signal is active. A new data loaded to the circuit each time the "Ld" (4.0) n shift count 5-bit down counter CLK Decr Ld n-04.00 signal activated. The output "n" is equal to "1" in case the count value reaches "00000". Explain why the control unit needs such circuit. n-0 Do functional simulation for your design. Figure 2 D-

Draw block diagrams to implement a 4 to 1 with 4 bits multiplexer. The data input lines are 4 bits wide. Please decide how many selects do you need. And write the final equation for inputs and output in both your report and block diagram. Do the simulation and save the screenshot into your report.

solve 2 and 3 only thanks

Code a program in assembly language that sets the carry bit in the flag register. Make sure to read the flag register in the rcx register and to use a debugger to confirm if carry flag and zero flags are set.

The interrupt vector table stores a different set of information for each entry.

Design a two-bit binary counter with a single input x. When the input x=0, the counter stopscounting and when the input x=1, the counter continues counting. In your design use JK flipflops. Show the state diagram and the state table.   https://www.bartleby.com/questions-and-answers/design-a-two-bit-binary-counter-with-a-single-input-x.-when-the-input-x0-the-counter-stops-counting-/626ccbfb-139d-4915-ac6c-cefd6abe5667

Using timert in CTC mode and interrupts create a 50HZ square wave on pin 5. Use a prescaling of 256 define LedToggle digitalWrite void setup 0 ( pinMode / Disbale global interrupts initialization of control register A initialization of control register B // enable interrupts initialization of the output compare register //Enable global interrupts ISRO LedToggle void loop 0 0 OX0B 55536 OX0A TIMER1 COMPA vect Ox00 TIMER1 OVF vect INPUT Ox01 60536 Ox05 63036 65458 TCNT1 4 40000 sei() 625 TIMSK1 OCR1A 25536 65224 65380 1250 digitalRead 20000 156 45536 64286 21 TCCR1B 64911 312 6. 5000 digitalWrite OXOC OX0D 78 2500 OUTPUT TCCR1A 10000

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Figure 1.5(a) shows the Verilog implementation of a module digital_block with a clock input clk, a 10-bit input n[9:0] and an output out. (i) Sketch a block diagram showing the function of digital_block. (ii) This circuit is driven by a 50MHZ clock signal and an input N as shown in Figure 1.5(b). Sketch the output signal Y. State any assumption used. 1 module digital block(clk, n, out); // clock signal input input (9:0] output clk; n; out; reg [9:0] reg [5:0] cnt; reg out, tick; 10 11 initial v = 10 b0; initial cnt = 6'd49; 12 13 always e (posedge clk) if (cnt == 6' de) begin cnt <= 6'd49; tick <= 1'b13; end else begin 14 15 16 17 18 19 cnt <= cnt 1'b1: tick <= 1'be; end always @ (posedge tick) begin if (v < 10'd999) V <= v + 1'b1; else v = 10'do; out <= (v < n): end 31 endmodule Figure 1.5(a) digital_block 750 N n[9:0] 250 outEY 4ms 8ms 50MHZ clk Figure 1.5(b) 2~~~ 22Mm m

Question [5]: Design a 3-bit synchronous counter which counts according to the following sequence 001 ® 110 ® 010 ® 101 ® 000 ® 111 and repeats. Design the counter using Two D-FF and One JK-FF such that the JK is the middle flip flop. What is the next count if the counter started with 011 (unused state)?