Write down the Input / Biasing Equation: Using voltage divider, calculate the voltage, VB. Calculate the voltage, VE. Assume VBE = 0.7 V. Calculate the current, IC. Assume IC and IE. Write down the Output / DC load line Equation: Calculate VCE. Calculate the Amplifier Open-circuit Voltage Gain: AV(OC) = (Vout(OC)(PP) / Vin(PP)) =

Q3) The Voltage-divider bias circuit shown below is to be designed to operate efficiently stabilized. Assume Ic(max) = 16mA and VRE= CC: 1) Find the values of R₁, R2, RE, Rc for maximum output voltage swing. 2) Draw the d.c. load line and a.c. load line on same graph indicating the Q point (VCEQ, Ico). 3) Determine the maximum value to which Vcc can be adjusted without exceeding a rating assuming PDmax=400m W Best wishes from me Barwan Ahmed 10 Vino C₁ R₁ www Vcc +20V R2 Rc C3 Si Tr B=100 Vou RL 1k

Q2

Diagram show biasing by feedback resistor method.Calculate (i) collector current, and (ii) collector voltage, Given that ß = 100 and transistor is made of sillicon.

homework multistage Homework: Consider the circuit shown in Figure below with transistor parameters ß 120 and VA =o. (a) Determine the small-signal parameters gm, r, and I, for both transistors. (b) Plot the de and ac load lines for both transistors. (c) Determine the overall small-signal voltage gain Av = vo/vs. (d) Determine the input resistance R and the output resistance Ro. (e) Determine the maximum undistorted swing in the output voltage. Vcc = +12 V RCI = R3= R3 = 15 kQ 10 k2 Ris Ca 67.3 k2 R. Cc3 Deadline: 7-5-2022 SR, = 12.7 k2 REI 45 k2 CE RE2= 3 RL = 1.6 k2 3 250 2 32 k2 ww w

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A. For the configuration shown below in 4(A), find the small signal voltage gain (Voutp-Voutm)/Vin B. For the configuration shown in 4(B), find the following parameters (a) DC value of output voltage, (b) input common mode range and (c) small signal voltage gain when all transistors are in saturation vou/Vin as indicated in the diagram; Assume no body bias on M1 ad M2 For this problem ONLY, assume the following device parameters V7, = \V| = 0.5V;K, = k ,' = 100 µA / V²,a, = a, = 0.01 VDD = 3V (10/1) M, M. (10/1) (10/1) M, |M, (10/1) Voutp 20kΩ м, (200/1) м, м, (10/1) м, Vin (1/1) м, M. (10/1) + Vin DC VAN M, 100HA (1/1) M, M, (10/1) (A) (B) V. =-1V

answer part b,c, and d

2) Consider an enhancement MOSFET common source amplifier circuit in Figure 2(a). The output characteristic is showed in Figure 2(b). Assume that the circuit is operating in the saturation region and k = 5 mA/V2. It also given that ra = ro = 00, Cgd = 2 pF, Cgs = 4 pF, Cas = 1 pF, Cwi = 4 pF and Cwo = 3pF. a. Using DC load line, prove that Ino = 22.5 mA and VpsQ = 5.5 V for Vaso = 2.5V. (Please attach the characteristic graph provided in your working solution) b. Draw the AC equivalent circuit at mid frequency. c. Estimate the voltage gain Av = Vo /Vi. d. Determine the dominant high cut – off frequency for the circuit. 10 V Rp 100 2 6 MQ C2 ci Rs RL Vo 1002 R: 5002 Rs Vo 14 MQ Cs 100 2 Vs Figure 2(a) 60- 50 30 20 10 9. 10 Figure 2(b) (yu) 4

For the p-channel JFET circuit in the Figure, the transistor parameters are: /oss = 2 mA, Vp = |1.75| V. (a) Determine Ipo and Vspo- (b) Give the small signal model (c) Determine the small-signal voltage gains Av = vo/vi QUESTION I: For the p-channel JFET circuit in the Figure, the transistor parameters are: Ioss = 2 mA, Vp = |1.75| V. (a) Determine Ipo and Vspo- (b) Give the small signal model (c) Determine the small-signal voltage gains Av = vo/vi VDD = 10 V Rg = 5 k£2 R1 = 90 kQ %3D Cc2 RL = 10 k2 R2 = 110 k2 ww