Write an 8-bit 16to1MUX module using an always block with case statement (RTL). Write a testbench to verify it. Write an 8-bit 4to1MUX module using an always block with case statement (RTL). Then instantiate 5 8-bit 4to1MUXs to make an 8-bit 16to1MUX shown below (Structural Ver 16tol Mux

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CSE224 HW#1
1- Write an 8-bit 16to1MUX module using an always block with case statement (RTL).
2- Write a testbench to verify it.
3- Write an 8-bit 4to1MUX module using an always block with case statement (RTL).
4- Then instantiate 5 8-bit 4to1MUXs to make an 8-bit 16to1MUX shown below (Structural Verilog).
16tol MuX
8-bit
is
out
out
i15
5- Verify your second 8-bit 16to1MUX using the same testbench (step2).
6- Submit your Verilog code for mux designs and the testbench or just give us the share link of your
edaplayground project.
Transcribed Image Text:CSE224 HW#1 1- Write an 8-bit 16to1MUX module using an always block with case statement (RTL). 2- Write a testbench to verify it. 3- Write an 8-bit 4to1MUX module using an always block with case statement (RTL). 4- Then instantiate 5 8-bit 4to1MUXs to make an 8-bit 16to1MUX shown below (Structural Verilog). 16tol MuX 8-bit is out out i15 5- Verify your second 8-bit 16to1MUX using the same testbench (step2). 6- Submit your Verilog code for mux designs and the testbench or just give us the share link of your edaplayground project.
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