When we short Vsig , Rsig why does not shrorted and it should be apart of the source ?

Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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When we short Vsig , Rsig why does not shrorted and it should be apart of the source ?
VDD
Secondly, We will consider C,:
RD
Cel
1. Set Vsig = 0
ww
2. The other two
V.
sig
capacitors are
short circuits.
3. Finding resistance between Capacitor terminals:
-V
SS
ro
+ [Rp||RL]
1+ gmro
4. Finding the pole frequency associated with that capacitor through the terminal of
the capacitor :
S
ro
+ [Rp||RL]
ww-
Transcribed Image Text:VDD Secondly, We will consider C,: RD Cel 1. Set Vsig = 0 ww 2. The other two V. sig capacitors are short circuits. 3. Finding resistance between Capacitor terminals: -V SS ro + [Rp||RL] 1+ gmro 4. Finding the pole frequency associated with that capacitor through the terminal of the capacitor : S ro + [Rp||RL] ww-
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