When an instruction was CORRECTLY executed on the MIPS single-cycle CPU, we observed MemtoReg = 0, RegDst = 0, and MemWrite = 0. Select all the correct answers below: %3D This instruction might be sw This instruction MUST NOT be sw This instruction MUST be addi This instruction might be addi This instruction might be slt This instruction might be beq This instruction MUST NOT be Iw

Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter6: System Integration And Performance
Section: Chapter Questions
Problem 33VE
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I need someone who is good with mips programming please!

Q1 MIPS single-cycle CPU
10 Points
MemteReg
MemWrite
Control
Unit
Branch,
ALUControl
PCSrc
31:28
Op.
Fund
ALUSre
RegDst
Deghnte
CLK
CLK
CLK
WE3
RD1
SrcA
Zero
WE
25215
A1
PC
PC
Instr
RD
ALUResult
ReadData
RD
A.
Instruction
Memory
Data
Memory
WD
A2
RD2
SrcB
A3
WriteData
Register
File
WD3
WifeReg..
PCPlus4
Senimm
Sign Extend
PCBranch
Resut
01.11w instruction execution.
4 Points
hematic when lw $8. 4(S9) is executed select all the
Transcribed Image Text:Q1 MIPS single-cycle CPU 10 Points MemteReg MemWrite Control Unit Branch, ALUControl PCSrc 31:28 Op. Fund ALUSre RegDst Deghnte CLK CLK CLK WE3 RD1 SrcA Zero WE 25215 A1 PC PC Instr RD ALUResult ReadData RD A. Instruction Memory Data Memory WD A2 RD2 SrcB A3 WriteData Register File WD3 WifeReg.. PCPlus4 Senimm Sign Extend PCBranch Resut 01.11w instruction execution. 4 Points hematic when lw $8. 4(S9) is executed select all the
Q1.2 HW signal matching instructions
3 Points
When an instruction was OCORRECTLY executed on the MIPS single-cycle CPU, we observed
MemtoReg = 0, RegDst = 0, and MemWrite = 0, Select all the correct answers below:
This instruction might be sw
This instruction MUST NOT be sw
This instruction MUST be addi
This instruction might be addi
This instruction might be slt
This instruction might be beq
This instruction MUST NOT be lw
Provide your expianations for each of the options(why it is corect or incorrect),
43 P
Transcribed Image Text:Q1.2 HW signal matching instructions 3 Points When an instruction was OCORRECTLY executed on the MIPS single-cycle CPU, we observed MemtoReg = 0, RegDst = 0, and MemWrite = 0, Select all the correct answers below: This instruction might be sw This instruction MUST NOT be sw This instruction MUST be addi This instruction might be addi This instruction might be slt This instruction might be beq This instruction MUST NOT be lw Provide your expianations for each of the options(why it is corect or incorrect), 43 P
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