We can design 3-8 decoder from two 2-4 decoders when connected in the fallowing circuit: Option 2 Non of them A A decoder GIA O Fig Option 3
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- Q3/ Design maximum size multiplexer by using the following (Note that all multiplexers and all decoders active low multiplexers. enable) Type of multiplexer 8-to-1 4-to-1 2-to-1 Number of multiplexers 3 3 10 Type of decoder 3-to-8 2-to-4 1-to-2 Number of decoder 1 4 6Arrange the chronological order of the elements and its function to Digital Communication by writing the numbers 1 to 10 in both column A and column B. A Elements Channel Decoder Channel Encoder Digital Demodulator LICHTE SE Digital Modulator Input Transducer Channel Output Signal Output Transducer Source Source Decoder Source Encoder B A ndeseng Function After detecting the sequence, it does some error corrections. A It can be an analog signal. It compresses the data into minimum number of bits. It converts the signal into the original physical form, which was at the input of the transmitter. It does the coding for error correction. It allows the analog signal to transmit from the transmitter end to the receiver end. It produced after the whole process. It takes a physical input and converts it to an electrical signal. The received signal is demodulated as well as converted again from analog to digital.notni erli lo ini arli lo voeber edirsin.sm The resultant signal is once again…Question) Why need Analog to Digital and wice we Nersa conversion im below mentione d prncess? we elininale these steps process: Esiplain Can in this with reasons? cD Foligonai, Digital-to.anala> Linear amphitic. con ver hor speaker.
- Which statement is true about index of modulation? a. Vmin is positive in undermodulation b. Vmin is zero in undermodulation c. the peak carrier voltage is less than the peak modulating voltage d. Vmin is negative in undermodulation(a) Explain the main different between a 2-bit asynchronous counter and a frequency divider by 4 with the aid of appropriate diagram. (b) Determine the sequence of the counter shown in Figure 7 and explain the function of NAND gate in the circuit. Begin with the condition that the counter is cleared. Show the appropriate waveforms for all input and outputs to support your answer using the answer sheet provided in Appendix. Do D D2 CLK Figure 7 |Rajah 7) (c) Design a synchronous counter that can count up and down for a sequence of 3+2+»5+>1 using D flip-flops.Design an encoding matrix with diodes and resistors to display a decimal number to on the seven-segment display. You have 10 switches (WO-W9) with one terminal connected to Vec. For decimal number 0, switch 0 (S0) is closed, for decimal number 1, switch 1 (S1) is closed etc. (Switches are on the vertical axis, S0 on top and the outputs are taken on the horizontal axis (Y0-Y6), with “a" on the left and "g" on the right. Note that (Y0-Y6) outputs are used as inputs to seven-segment display. Since these outputs cannot drive the seven segment display LEDS you may need additional bipolar transistors and resistors. The supply voltage is 5V and each LED needs a current of 20mA. Note that this is a design problem and the design is not unique. Do your best! f a a e
- Match the correct multiplexer output given the select lines. Hb G F E D- C MUX 4₁ 1。 MUX lo MUX 1。 B AL MUX S₂ "S2 = 1, S1 = 0, S0 = 0" ✓ "S2 = 1, S1 = 1, S0 =0" ✓ "S2 = 0, S1 = 1, S0 =0" ✓ "S2 = 0, S1 = 0, S0 = 1" ✓ "S2 = 0, S1 = 0, SO = 0" ✓ "S2 = 1, S1 = 0, S0 = 1" ✓ "S2 = 0, S1 = 1, S0 = 1" "S2 = 1, S1 = 1, S0 = 1" 10 MUX MUX 4 S₁ 16 MUX So Z A. F B. A C.E D. D E. H F. G G.C H.BQ2-A-For VCO-LO that represent FM-TX if frequency of the carrier signal at -5 volt. Calculate the frequency deviation Af * signal MESSAGE VT SIGNAL 119 (M) NEGATIVE SUPPLY OSCILLATOR 2v. BUFFER 5 KHz VEC (-12 Vdc) VCO-LO circuit block schematic. (FM) VT [volt] -1 -2 -3 -5 -6 -7 -9 -10 FM Output 500 505 510 515 520 525 530 535 540 545 Freq [kHz] O 10 KHz O O 20 KHzWhat is a JFET? Explain its construction and describe the biasing methods available for biasing a JFET? Please don't write on paper