This makes it more probable that applications written for 0-, 1-, and 2-address architectures will be more involved (have more instructions). Why?

Computer architecture

Discuss the concept of superscalar and VLIW architectures in relation to instruction-level parallelism. How do these architectures exploit parallelism in instruction execution?

Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain in bytes/s? To increase its performance, would it be better to make its external data bus 32 bits or to double the external clock fre- quency supplied to the microprocessor? State any other assumptions you make and explain. Hint: Determine the number of bytes that can be transferred per bus cycle.

What is the purpose of address decoding and explain the difference between full andpartial address decoding. Assuming the address bus is 16-bit wide, using the addresslines with no additional logical gates, how many 1024-Byte memory devices could besupported if each has a single Chip-Enable pin? Explain your answer.

How does "cache hierarchy" impact the performance and efficiency of a pipelined architecture?