The terms "unified cache" and "Hadley cache" need to be clarified.
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- "Hadley cache" and "unified cache" need to be described in terms of what they mean.The difference between a fully associative cache and a directly mapped cache is worth considering.For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. a. What is the cache block size in words? b. How many entries does the cache have? Tag 31-13 Index 12-6 Offset 5-0
- For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache: Tag Index Offset 31-10 9-6 5-0 1. What is the cache block size (in words)? 2. How many entries does the cache have? 3. What is the ratio between total bits required for such a cache implementation over the data storage bits?What are the three fields in a set-associative cache address, and how are they used to access a location in cache?What is the definition of completely associative cache?
- Clarify "unified cache" and "Hadley cache".For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 a. What is the cache block size (in words)? b. How many entries does the cache have? Offset 4-0 c. What is the ratio between total bits required for such a cache implementation over the data storage bits?What is the advantage of a nonblocking cache?