The figure below shows a series of JK flip flops which are triggered by the rising edge of the clock signal. VCC B J A J ciciel CLK B K C J CLK K VCC CLK A K VCC Draw a diagram making the required connection changes, and adding any required logic gates to the above circuit such that it: Counts in the opposite direction (e.g. down, if it counted up previously, or up if it counted down previously) And resets at the number 6 (a mod 7 counter), using the same flip flops and settings as before (rising edge triggered, no propagation delay, clk signal starting low).

Make a capture of a two-bit down flip flop counter: first counter from 0 to 6 (jumping one) and second counter from 0 to 7 (jumping one) with flip flop jk

1) The following waveform are applied to the J-K flip flop with negative edge clock pulse. Assuming the flip flop is initially set, determine the Q output. (a) 2) Repeat question 1 for positive edge clock pulse.

The question is appended to the image.  I don't understand what the question is asking, nor how to implement a d flip flop as required.