The design team for a simple, single-issue processor is choosing between two pipelined implementations. Here are some design parameters for the two possibilities: A B Clock Rate (MHz) 3500 2250 1 1 CPI for ALU instructions CPI for Control instructions CPI for Memory instructions 3.0 1.5 2.5 1.1 For a program with 20% ALU instructions, 15% control instructions and 65% memory instructions, which design will finish first? Give a quantitative CPI average for each case.

Suppose we had a processor design with 5 stages where each stage takes the following amount of time: IF: 400 ps ID: 200 ps EX: 300 ps MEM: 500 ps WB: 200 psQ1: If you choose a pipelined design, what is the CPI? Assume that we have enough instructions such that the brief ramp up period at the beginning and the ramp down period at the end with less than 100% utilization does not matter. Q2: If you choose a pipelined design, what is the average execution time per instruction in picoseconds?