The debate is whether SIMD is better suited to data or control-level parallelism. When it comes to parallelism at the programme level, what kind is best appropriate for MIMD?

How do pre-fetching and caching mechanisms work in tandem with pipelining to enhance performance?

An example of a MISD machine is referred to as a systolic array. A set of data processing components that are linked together in the form of a pipeline network or "wavefront" is referred to as a systolic array. Because the execution of each of these components is kicked off by the reception of data, each of these components is self-contained and does not need a program counter. Calculations are performed in "lock-step" by systolic arrays that have clocks that are synchronized, with each CPU executing alternate phases of computation and communication.

Systolic arrays, a kind of array, include MISD machines. A networked pipeline of data processing equipment is a systolic array. No programme counter is needed since execution is started by fresh data. Each timed systolic array unit computes and communicates in unison, isn't that correct?

When it comes to a processor's access to main memory, the loosely connected setup and the symmetric multiprocessing configuration are similar. Explain why, in the real world, the symmetric design might be better.

Which kind of program-level parallelism, data or control, is more ideally suited for the SIMD instruction set? Which kind of program-level parallelism does MIMD lend itself most well to?

What is the speedup of a system where 4/5 of the execution time benefits from parallelism and the number of parallel nodes is 4? What if the number of nodes is 8? What if the number of nodes is 16?

Control or data parallelism, which sort of program-level parallelism works better with one instruction many data? Which technique to parallelism at the program level is most suited for MIMD?

Understand the distinction between parallel and serial programming.

Discuss the concept of superscalar and VLIW architectures in relation to instruction-level parallelism. How do these architectures exploit parallelism in instruction execution?