Signals in VHDL A VHDL design has five input ports labeled enable (MSB), read, write, selector, and compare (LSB) and three outputs labeled address_latch (MSB), data_enable, and strobe (LSB). a. Write a VHDL statement that concatenates all input lines into a signal called control. The signal is written with the most significant bit on the left. b. Write a series of VHDL statements that separates a signal called status into the output ports listed above. The ports are written with the most significant bit on the left.

Design a 4-bit Asynchronous Counter up/down (Note: Please have the design be a clear outline or printed in order to attach it to the file)

1. A multiplexer is a device that selects one among N analog or digital inputs and forwards the selected input to a single output line. Answer the following questions. (Note: You should show all the steps to receive full credits) a) If the mux has 4 inputs, how many control inputs are needed? b) Draw the truth table of 4-to-1 multiplexer. |

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