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- Logic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions.Task 1: 2-to-1 LINE MULTIPLEXER DESIGNA) Write the truth table of 2-to-1 line multiplexer.B) Draw the circuit diagram by using only NAND & NOT GATES.C) Simulate the circuit that you found in part B.Logic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions. Task 2: 4 INPUT PRIORITY ENCODERa) Write the truth table.b) Find the outputs in terms of min terms using minimal expression.c) By using K map, find the simple/simplest expression of theoutputs.d) Draw the circuit diagram. (Simulation design will be accepted.)e) Simulate the circuit & explain your results. (Please do notdesign separate simulations for each output. You should design ONEsimulation including all inputs and outputs.)We want to design a circuit to detect prime numbers.The input of the circuit is a 4-bit binary number and the output is a single bit and should show one when the number is prime and zero otherwise.B. Implement the circuit using a 4× 1 multiplexer and combinational logic gates.C. Implement the circuit using only one decoder and one OR gate. What is the size of the decoder you use?
- The numbers from 0-9 and a no characters is the Basic 1 digit seven segment display * .can show False True In a (CA) method of 7 segments, the anodes of all the LED segments are * "connected to the logic "O False True Some times may run out of pins on your Arduino board and need to not extend it * .with shift registers True False4. A data signal with bipolar voltage levels is shown below. The decision threshold is 0 volts. The logic levels are +1 volt for logic 1 and -1 volt for logic 0. Noise with the P.D.F. shown corrupts the signal. Find the probability of error at some instant of time on the condition that logic 0 is sent. LOGIC 1 +1 VOLT -2 1/2 دمت ~IN kla THRESHOLD +2 NOISE P.D.F. -I VOLT. LOGIC 0Design a 7-bit counter. (It can be a synchronous or asynchronous counter.) This counter is requested to be reset when it reaches the number 62 . Make the necessary changes to the counter to provide this desired feature.
- Q1. Read the following description concerning a logic circuit, and then answer Subquestions 1 and 2. Figure 1 shows a logic circuit that is used as a control system for an electronic device. The logic circuit has three inputs (X, Y and Z) and one output (F). As shown in Figure 1, the logic circuit has a feed back line, by which the last output F is fed back and is used as the current input to the NAND gate. Therefore, the current output F is determined by three current inputs X, Y and Z and the last output F. In this control system, among three inputs X, Y and Z, at most only one input can change its value on each clock cycle. (Feed back line) Figure 1 The logic circuit Meanings of the logic gate symbols used in Figure 1 are as follows: AND gate NAND gate OR gate NOR gate Figure 2 shows sample input/output status of the logic…d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.6. F in the blanks in the truth table of the given digital circuit NOT Use fer NOT gate egX. Use paranthesis only for combining two logic gates OR and AND e ZOX+Y) er (Y+Z).OX+Y) You can use either XY or X.Y for AND gate. Write the letters in alphabetic orders: eg XY, not YX 1 5
- The logic circuit: (From minimum SOP) Number of gates used in the circuit: 2-Input AND gate.. 2-Input OR gate. NOT gate Number of idle gates in the chip: 2-Input AND gate 2-Input OR gate... NOT gute The logic circuit: (From minimum POS) gates gates gates gates gutes Number of gates used in the circuit: 2-Input AND gate 2-Input OR gate... NOT gate Number of idle gates in the chip: 2-Input AND gate... 2-Input OR gate, NOT gate, IC name: IC name: IC name: gates IC name: gates IC name: gates IC name: gates gates gates(a) Given an arithmetic function Y = 4A – B. Design a module that can perform the computation for the arithmetic function using the minimum unit of 4-bit adder only. Do not ignore the borrow output. You just need to show the block diagram. Do not show the gate level logic circuit. Clearly show the interconnections and input output labels. (b) Prove the circuit in Figure Q.5 can perform the operation of adder/subtractor by completing Table Q.5. a, a, b, Sub FA FA FA FA Co Figure Q.5 Table Q.5 Sub A[3:0] B[3:0] C4 S[3:0] Operation 0111 1000 1 0111 1000Act 1 problem solving this is a logic circuits and design laboratory subject please help me with this and screenshot all the solution and answers 2. What is the largest binary number that can be expressed with 16 bits? What are the equivalent decimal and hexadecimal numbers? Answer: 16 bits = ________= _______10 = ______16 3. Represent the decimal number 6,248 in: (a) BCD = (b) excess‐3 code = (c) 2421 code =