Question 5. Consider the implementation of a logic function using a decoder given in figure 2 and answer the below questions.

16) Answer each of the following with reference to the overfill alarm program shown in the figure below. a. Assume that the vessel is filling and has reached the 300-lb point. State the status of each of the logic rungs (true or false) at this point. b. Assume that the vessel is filling and has reached the 480-lb point. State the value of the number stored in each of the following words at this point: (1) I:012 (2) N7:1 c. Assume that the vessel is filled to a weight of 502 lb. State the status of each of the logic rungs (true or false) for this condition. d. Assume that the vessel is filled to a weight of 510 lb. State the value of the number stored in each of the following words for this condition: (1) I:012 (2) N7:1 18 e. With the vessel filled to a weight of 510 lb, state the status of each of the logic rungs (true or false). Inputs Ladder logic program Ouputs Fil Stop Start Full solenoid L2 Fill Fil solenoid solenoid Fill Filing solenoid Filing Full Ful GEQ GREATER THAN OR EQUAL…

Combinational Circuits - Design Procedure Design a logic circuit that has three inputs A, B, C and whose output will be HIGH only when a majority of the inputs are HIGH. 3-A. Generate the truth table. 2-B. Obtain the KMAP. 3-C. Provide the Simplified Boolean Function. 3-D. Generate the Logic diagram of the simplified Boolean function.

show how to design a 8-bit Function Unit Combining Arithmetic Logic Unit (ALU) and a Shifter that can perform the operations given in table 1 below. Use X and Y as 8 bits input and F as 8 bits output as shown in Figure 1. S0,S1,S2 and S3 represent the selction code in the operation set table Three statue bits V (over flow), C (carry), N (negative) and are related to arrithmatic operations and statue bit Z (zero) is relataed to both arrithmatic and logic operation. Test your designed Function Unit with necessary tables.

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Question 6a and b are: Draw the logic diagram for the following Boolean expression. Then simplify the Boolean expression in (a) using a karnaugh map. The picture goes into more details about the assignment.

Draw the AND and OR gate logic diagram of the expression. X=[[K(K+L) +M] Logic diagram using AND-OR gates Redraw the circuit using positive NOR gates. Logic diagram using positive NOR gates

Sometimes "bubbles" are used to indicate inverters on the input lines to a gate. What are the equivalent gates for those shown in the figure below? Hint - use DeMorgan's Law. A B C=A+B (a) D F=DE E (b)

Can the expert draw a full adder gate?