QUESTION 4 Two D fip flops are connected in Fig 4 with the timing dagrams for input CLK and D. D D1 Q1 D2 Q2 CLK CLK CLK Fig 4 CLK D Q1 Q2 Draw the wavetorm outputs at 01 and 02. ... ... ..... ... ...

3. The waveforms shown in Figure below are applied to a negative edge-triggered JK flip- flop. The flip-flop's Preset and Clear inputs are active LOW. Complete the timing diagram by drawing the output waveforms. CLK J PRE CLR Q

For the frequency divider circuit the D-flip-flop is a CD4013 Dual D-Type flip-flop V2 is a square wave applied to the Clock input and Q is the ouput waveform. a. What is the frequency of the square wave Clock from V29? b. What is the frequency of the output pin Q? c. How many D-flip-flops are implemented in the CD4013 Chip? d. How many outputs are implemented in each D-flip-flop? List them.

The circuit shown below is supposed to be a 3-bit ripple counter, but when it is tested it is seen that only the first chip, U0, has an output that changes as it should.  Q1 and Q2  are both at constant values of 0.  The JK flip-flops are not defective, so there is a problem with the wiring of the circuit.  Assume that the SET and RESET inputs to the JK flip-flops are all connected to HIGH. Explain what is wrong with the wiring of the circuit and how you would change the wiring so that the counter works correctly.  Make sure to clearly identify what part of the circuit you are referring to.