Question 2. Refer to the single-cycle computer in Figure 1, shown at the end, and the instruction specifications for the simple computer in table 1, do the following: a) Complete the following table, giving the binary instruction decoder outputs from Figure 2 during execution of each of the instructions: [10] Instruction-Register Transfer Opcode DR SA SB or Operand R[4] ER[2] - R[1] M[R[4]] < R[5] R[2]< R[7] + 3 R[3]
Question 2. Refer to the single-cycle computer in Figure 1, shown at the end, and the instruction specifications for the simple computer in table 1, do the following: a) Complete the following table, giving the binary instruction decoder outputs from Figure 2 during execution of each of the instructions: [10] Instruction-Register Transfer Opcode DR SA SB or Operand R[4] ER[2] - R[1] M[R[4]] < R[5] R[2]< R[7] + 3 R[3]
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Question
Plz solve all parts.Plz solve in 90 minutes
![B Page view |A Read aloud | V Draw
E Highlight
-
Question 2. Refer to the single-cycle computer in Figure 1, shown at the end, and the instruction
specifications for the simple computer in table 1, do the following:
a) Complete the following table, giving the binary instruction decoder outputs from Figure 2 during execution of
each of the instructions: [10]
Instruction-Register Transfer
Opcode
DR
SA
SB or Operand
R[4] ER[2] - R[1]
M[R[4]] < R[5]
R[2]< R[7] + 3
R[3]<R[4] O R[3]
R[1] ER[2] + R[3]
+](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F6fbe6715-6f88-4967-bf2e-57d931e1b6d6%2Fe3f3e489-3bec-44cf-8a2e-ae4bc4b5d94f%2Focjtu5_processed.png&w=3840&q=75)
Transcribed Image Text:B Page view |A Read aloud | V Draw
E Highlight
-
Question 2. Refer to the single-cycle computer in Figure 1, shown at the end, and the instruction
specifications for the simple computer in table 1, do the following:
a) Complete the following table, giving the binary instruction decoder outputs from Figure 2 during execution of
each of the instructions: [10]
Instruction-Register Transfer
Opcode
DR
SA
SB or Operand
R[4] ER[2] - R[1]
M[R[4]] < R[5]
R[2]< R[7] + 3
R[3]<R[4] O R[3]
R[1] ER[2] + R[3]
+
![O TABLE 1
Instruction Specifications for the Simple Computer
Mne-
Opcode monic
Status
Instruction
Format
Description
Bits
R[DR]+ R[SA]*
R[DR] + R[SA] + 1*
RD, RA, RB R[DR]+R[SA] + R[SB]*
RD, RA, RB R[DR]+ R[SA] – R[SB]*
R[DR]+ R[SA] – 1*
RD, RA, RB R[DR]+ R[SA] ^ R[SB]*
RD, RA, RB R[DR]+ R[SA] v R[SB]*
RD, RA, RB R[DR]+R[SA] ® R[SB]*
R[DR]+ R[SA]*
R[DR]+ R[SB]*
R[DR] + sr R[SB]*
R[DR] +sl R[SB]*
R[DR]+zf OP•
RD, RA, OP R[DR]+R[SA] + zf OP*
R[DR]+ M[SA]*
M[SA]+ R[SB]*
Move A
0000000 MOVA RD, RA
N, Z
N, Z
N, Z
Increment
0000001 INC
RD, RA
Add
0000010 ADD
Subtract
0000101 SUB
N, Z
N, Z
N, Z
N, Z
N, Z
Decrement
0000110 DEC
RD, RA
0001000 AND
0001001 OR
AND
OR
Exclusive OR
0001010 XOR
0001011 NOT
0001100 MOVB RD, RB
NOT
RD, RA
N, Z
Move B
Shift Right
0001101 SHR
RD, RB
Shift Left
Load Immediate
0001110 SHL
RD, RB
1001100 LDI
1000010 ADI
RD, OP
Add Immediate
N, Z
Load
0010000 LD
RD, RA
Store
0100000 ST
RA, RB
Branch on Zero
1100000 BRZ
RA, AD
if (R[SA] = 0) PC+ PC + se AD, N, Z
if (R[SA] = 0) PC – PC + 1
Branch on
1100001 BRN
RA, AD
if (R[SA] <0) PC + PC + se AD, N, Z
Negative
Jump
if (R[SA] 20) PC – PC + 1
PC R[SA]
1110000 JMP
RA
* For all of these instructions, PC + PC +1 is also executed to prepare for the next cycle.
COMPUTER DESIGN BASICS](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F6fbe6715-6f88-4967-bf2e-57d931e1b6d6%2Fe3f3e489-3bec-44cf-8a2e-ae4bc4b5d94f%2Ftimrn9h_processed.png&w=3840&q=75)
Transcribed Image Text:O TABLE 1
Instruction Specifications for the Simple Computer
Mne-
Opcode monic
Status
Instruction
Format
Description
Bits
R[DR]+ R[SA]*
R[DR] + R[SA] + 1*
RD, RA, RB R[DR]+R[SA] + R[SB]*
RD, RA, RB R[DR]+ R[SA] – R[SB]*
R[DR]+ R[SA] – 1*
RD, RA, RB R[DR]+ R[SA] ^ R[SB]*
RD, RA, RB R[DR]+ R[SA] v R[SB]*
RD, RA, RB R[DR]+R[SA] ® R[SB]*
R[DR]+ R[SA]*
R[DR]+ R[SB]*
R[DR] + sr R[SB]*
R[DR] +sl R[SB]*
R[DR]+zf OP•
RD, RA, OP R[DR]+R[SA] + zf OP*
R[DR]+ M[SA]*
M[SA]+ R[SB]*
Move A
0000000 MOVA RD, RA
N, Z
N, Z
N, Z
Increment
0000001 INC
RD, RA
Add
0000010 ADD
Subtract
0000101 SUB
N, Z
N, Z
N, Z
N, Z
N, Z
Decrement
0000110 DEC
RD, RA
0001000 AND
0001001 OR
AND
OR
Exclusive OR
0001010 XOR
0001011 NOT
0001100 MOVB RD, RB
NOT
RD, RA
N, Z
Move B
Shift Right
0001101 SHR
RD, RB
Shift Left
Load Immediate
0001110 SHL
RD, RB
1001100 LDI
1000010 ADI
RD, OP
Add Immediate
N, Z
Load
0010000 LD
RD, RA
Store
0100000 ST
RA, RB
Branch on Zero
1100000 BRZ
RA, AD
if (R[SA] = 0) PC+ PC + se AD, N, Z
if (R[SA] = 0) PC – PC + 1
Branch on
1100001 BRN
RA, AD
if (R[SA] <0) PC + PC + se AD, N, Z
Negative
Jump
if (R[SA] 20) PC – PC + 1
PC R[SA]
1110000 JMP
RA
* For all of these instructions, PC + PC +1 is also executed to prepare for the next cycle.
COMPUTER DESIGN BASICS
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