QUESTION 12 Which of the following instructions will disable all of the interrupts? O a. SEI Ob. RETI Oc cu d. ANDI QUESTION 13 If serial data can be transmitted and received, but only one way at a time, this is known as Oa synchronous O b. simplex C. full duplex d. half duplex QUESTION 14 In the RS232C serial interface standard, the logic 1 is represented by which signal levels? Oa.-3 to -25 V Ob.0 to 1.5 V Oc 3.5 to 5 V O d. 12.5 to 15 V QUESTION 15 The BAUD rate for the UART in the ATmega328PB is set in which UART registers group? Oa. Baud Speed registers Ob. Status registers Oc Configuration registers O d. Transmit and Receive registers QUESTION 16 The serial port flag that needs to be monitored so that the register containing data in the UART is not overwritten before the serial operations are complete is Oa. RXENO Ob. UDREO OC UCSROB Od.UPRO

QUESTION 12 Which of the following instructions will disable all of the interrupts? O a. SEI Ob. RETI Oc cu d. ANDI QUESTION 13 If serial data can be transmitted and received, but only one way at a time, this is known as Oa synchronous O b. simplex C. full duplex d. half duplex QUESTION 14 In the RS232C serial interface standard, the logic 1 is represented by which signal levels? Oa.-3 to -25 V Ob.0 to 1.5 V Oc 3.5 to 5 V O d. 12.5 to 15 V QUESTION 15 The BAUD rate for the UART in the ATmega328PB is set in which UART registers group? Oa. Baud Speed registers Ob. Status registers Oc Configuration registers O d. Transmit and Receive registers QUESTION 16 The serial port flag that needs to be monitored so that the register containing data in the UART is not overwritten before the serial operations are complete is Oa. RXENO Ob. UDREO OC UCSROB Od.UPRO

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 4RQ

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