Q4. What is the minimum number of NAND gates required to implemen A+A B+ABC? (a) 0 (b) 1 (c) 4 (d) 7

1. Realize the function a) By basic gates b) By NAND gates only c) By NOR gates only F = B'C' + A'C' + A'B'

Clock X C A D JEST B Y FIGURE 4-49 Circuit for Problem 4-11, Problem 4-40, Problem 4-41, Problem 4-49, Problem 4-50, and Problem 4-59 4-11. A sequential circuit has two D flip-flops, one input X, and one output Y. The logic diagram of the circuit is shown in Figure 4-49. Derive the state table and state diagram of the circuit.

Q4

5) Obtain a implementation of a half-adder circuit using standard gates such as AND, OR, NOT, XOR, etc. Obtain the minimal standard sum-of-products expressions for the Carry and Sum outputs of a half-adder. Compare these expressions with your implementation. PS:Please answer Number 6 after from number 5 6) Draw the schematic diagram of your implementation of the half adder from step 5).