Q4. For the combinational circuit shown below, list the truth table and find the equations of Fo, F, and F2. Where A, B, and C are the inputs whereas Fo, F1 and F2 are the outputs. (7682 IC is used to add a binary numbers of two bits). B FA Yo 7482 IC F2 Fo
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- (c) Figure Q3(c)(i) shows a register and Figure Q3(c)(ii) shows the input waveforms (CLOCK and Data in) to the circuit. A1 A9 A10 A2 Function generator A3 A11 A12 AS A13 A6 A14 A7 A15 Data in Bop.7) ip.r 82p.7) Logic analyser U1 U2 U3 U4 UO 6. 1. 6 1 6 INVERTER 3 CLK 3 CLK oCLK CLK 5 K K 5 K K 4027 Clock Function generator Figure Q3(c)(i) (i) Determine the type of register as shown in Figure Q3(c)(i).Solve the problem and simplify the output function using Quine–Mc Cluskey Methods. The following requirements must be met in solving the problem. Requirement:a. Truth Tableb. Timing Diagramc. Quine – Mc Cluskey Method d. Logic Diagram A private company wants to decide on a certain issue. Each of the four officials has an equal share of voting right. At least two of them must approve the solution in order to implement it. Each of them has a switch which closes to vote YES and open to vote NO.Logic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions. Task 2: 4 INPUT PRIORITY ENCODERa) Write the truth table.b) Find the outputs in terms of min terms using minimal expression.c) By using K map, find the simple/simplest expression of theoutputs.d) Draw the circuit diagram. (Simulation design will be accepted.)e) Simulate the circuit & explain your results. (Please do notdesign separate simulations for each output. You should design ONEsimulation including all inputs and outputs.)
- USE DIGITAL LOGIC AND DESIGN Part 1: In Figure_4; we have 4-bit Comparator using 2-bit Comparators block. You have to satisfy given condition by applying all data on figure 4. At the end, given condition should produce HIGH output and other two should be LOW. A3 A2 A1 A0 = 1101 and B3 B2 B1 B0 = 1110 Figure_4 Part 2: The serial data-input waveform (Data in) and data-select inputs (S0 and S1) are shown in Figure_5. Determine the data-output waveforms from D0 through D3. Figure_5 Part 3: Decoder can be useful when we have to decode some specific numbers from their equivalent code. Figure 6 has a concept of 3 to 8 line decoder from which you have to generate output waveform from D0 to D7 with proper relationship to input. Figure_6 Part 4: The data-input and…Task 6: Simplifying Boolean functions in EWB using the logic converter Simplify the following Boolean expression in EWB using the logic converter F (A, B, C) = AB'C'+ A'B'C'+ A'BC'+ A'B'CDISCUSSION: 1- Is the Gray code arithmetic code? Why? Where this code usėd? 2- What is the parity bit? 13- Design five - bit odd parity checker? 4- a) What are the main applications of the comparator? /b) Design two – two bit comparator. -5- Convert five.bit Gray to binary code, write truth table and draw the circuit diagram. 2-5
- 1) What is the biggest binary number (decimal value) you can write with 6 bits? What is the biggest binary number (decimal value and in terms of n) you can write with n bits? If you want to represent the decimal numbers from 0-16, what is the minimum number of bits you will need? Convert the decimal number 238 to binary number. (ZERO point if not showing steps/calculation!)1 - Design 3-bit Gray code generator 1-1 Construct the Truth Table of the 3-bit Gray code generator Logic Circuit. 1-2 1-3 1-4 Write down Standard SOP expression of the three output bits B2, B1, BO Without using minimization. Simplify the logic by using K-map. Write down the simplified expressions of B2, B1, B0. Sketch the logic circuit with basic gates.1. An arithmetic system operates with 3-digit decimal numbers with sign presented in BCD (12 bits), negative numbers utilize the 10's complement form, one decimal digit (4 bits) is occupied by sign: 0 for "+" and 9 for "-". 1a) Show the most positive and the most negative numbers in both decimal and BCD forms. 1b) Present numbers A=+36 and B= -42 in BCD. 1c) Present the 10's complements of A and B in BCD. 1d) Perform the following operations bit-by-bit, show carries, apply BCD correction (add 6) when necessary (the sum of two decimal digits is greater than 9). 1d1) A+B in BCD. 1d2) A - B = A+(-B) in BCD by addition of A and the 10's complement of B. 1d3) B-A= B + (-A) in BCD by addition of B and the 10's complement of A.
- 2.1 Combinational logic circuits. Tabulates a truth table for the following Boolean expression shown in Equation 1.1. f = A.B.C + A.B.C + A.B.C (1.1) 2.2 Half adder. A half adder is a circuit that adds two binary digits, A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition. Figure 1.2 depicted a logic diagram for a half adder. a. derives the Boolean expression for s and c. b. tabulates a truth table for the half adder. Ao Bo Figure 1.2: Half adder os S CDesign a code converter that converts a decimal digit from BCD to excess-3 code, the input variables are organized as (A BC D) respectively with A is the MSB, the output variables are organized as (W X Y Z) respectively with W is the MSB, put the invalid decimal numbers as don't care. X= BCD'+B'D+B'C X= BC'D'+B'D+BC X= BC'D'+B'D+B'C X= BC'D'+BD+B'CThis Question is from Digital Logic Design Q1. Assume your register number EF20BCE013 is in Hexadecimal, where014 are the three digits of your registration number.a) Represent your registration number in the binary.b) Split the ten digits of your registration into two Hexadecimal numbers M and N, where the leftmost five digits make number M and the right most five digits make number N. Using r’scomplement, subtract N from M. In other words, calculate M – N.