Q3/A/ The waveforms in Figure bellow are applied to the T-Flip Flop and clock inputs as Indicated, which change the output at falling edge (negative edge trigger). Determine the Q output, assuming that Q is initially LOW . யய ட CK T

Question 1 (Mandatory) If the a digital pattern repeats itself as 000111111100011111110001111111 .…...... the time interval for each logic state is 0.1 ms, what is the frequency and duty cycle of this digital waveform? 1 kHz, 30% duty cycle. 1 kHz, 70% duty cycle. 10 kHz, 70% duty cycle. 1 kHz, 80% duty cycle. Question 2 (Mandatory) The hexadecimal equivalent for decimal 922 is A93. 39A. 1093. 3910.

In a J - K flip-flip we have J = Q and K = 1. Assuming the flip flop was initially cleared and then clocked for 6 puleses, the sequence at the Q output will be (a) 010000 (b) 011001 (c) 010010 (d) 010101

Figure 2.1 shows the Asynchronous J-K flip flop and it truth table. Draw an output waveform, Q by drag and drop the correct waveform. Q is initially LOW. Clock Preset Clear Input J Input K Output J CLK K PRESET a Q CLEAR PRESET 1 0 CLEAR 1 1 0 0 Figure 2.1 FF response Clocked operation" Q1 (regardless of CLK) Q=0 (regardless of CLK) Not used 0 *Q will respond to J, K, and CLK