Q3: (A) Design a 4-to-16 decoder using 2-to-4 decoders with ENABLE input. (B) Design a synchronous counter that goes through the sequence: 0, 1, 3, 4, 6, 7 and gives an output Z=1 when the final count is reached using T flip-flops. Assuming the counter has the property of self-stopping.
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- Show how an asynchronous counter with negative edge-triggered D flip-flops can be implemented having a modulus-15. Draw the timing diagram for the counter including a decoder output signal.question from DIGITAL LOGIC DESIGN book Design a synchronous BCD Counter based on the following conditions. Design the Down counter with JK-Flip Flops by initializing the counter with 3 and count next five states. The counter should cycle back after counting five states. Perform all necessary designing stepsWe want to design a circuit to detect prime numbers.The input of the circuit is a 4-bit binary number and the output is a single bit and should show one when the number is prime and zero otherwise.B. Implement the circuit using a 4× 1 multiplexer and combinational logic gates.C. Implement the circuit using only one decoder and one OR gate. What is the size of the decoder you use?
- Show how an asynchronous counter with J-K flip-flops can be implemented having a modulus of eleven with a straight binary sequence from 0000 through 1010 . Draw the diagram.(need only handwritten solution .otherwise downvote.)Use D flip-flops to design a mod-16 binary down counter, whose counting sequence is 1111->1110->1101->1100->1011-> … ->0000->1111…. Derive the logic expressions for the D inputs of the flip-flops and draw the circuit diagram.Use D flip-flops to design a mod 5 counter. The counting sequence is 000->110->101->111- >001->000... (a) Draw the state diagram using 5 states; (b) Use CBA to represent the three bits of the state and write the state transition table; (c) Use K-maps to derive minimum sum-of-product equations for the flip-flop inputs.
- Design a 3-bit up/down counter using positive edge-triggered T flip-flops. Provide a respective timing diagram to justify the design. Show all the relevant working (state table, state diagram, K-maps, state equations, and final circuit diagram). An up/down counter has two inputs say x, y, and a clock signal. The output should increase by 1 if x = 1 and y = 0 on each rising edge of clock and decrease when x = 0 and y = 1 on each rising edge of clock. When x = y, the output should neither increase nor decrease on each rising edge of clock.Construct a synchronous 3-bit Up/Down counter with irregular sequence by using J-K flip-flops. The state diagram is shown below.Using two D flip-flops only, Design asynchronous Counter. The Counter counts in the sequence 1, 6, 3, 7, 1, 6, 37, 1,.. When its enable input x is equal to 1; otherwise, it is idle.
- Design a 4-bit ring counter using D flip-flop and draw the logic diagram of a 4-bit ring counter State Table: 4-bit ring counter (Shift Right) Present Next State State ABCA 001 B 0 10Design the asynchronous counter circuit using JK flip-flops, starting from the smallest decimal digit to the largest decimal digit in the following numbers. (1180501624)A binary pulse counter can be constructed byinterconnecting T-type flip-flops in an appropriatemanner. Assume it is desired to construct a counterwhich can count up to 10010. a. How many flip-flops would be required?b. Sketch the circuit needed to implement this counter.