Q1. Design asynchronous (ripple ) binary counter and timing diagram for the following sequence (0,1,2,3,4,5)

How could a binary-weighted DAC operate with BCD input? Explain.

An 8-bit DAC has a step size of 3mV.Determine the; I. Full scale output voltage And; II. Output voltage for the input of 11010111.

Please Follow Question List the outputs of Encoder at BCD indicators for each of the eight input pulses shown in Figure; (((Remember the activates of HIGH (1) that has a LOW (0) input.))): BCD output indicators 8s 4s 2s 1s D Encoder 3 B 6. 48 d9 (74147) 1 Add file

Q2: Answer the following: A- Sketch a block diagram of a 4-bit flash ADC and determine the binary code for each enable pulses of the encoder if the input analog samples for a number of enable pulses are 0.3, 4.1, 6.6 and 7.3. Take VREF = +8 V.

Question 4 For the given circuit shown in Figure Q4, answer the following questions: a) What is the functionality of this circuit? b) Why is priority encoder used instead of the regular (standard) encoder? c) What happens if R16 is an open circuit? What would be the output of the priority encoder? d) Modify the circuit to drive LEDS on the output without using the Priority encoder. Comparators Priority encoder Uis 15 14 13 12 11 10 8 Output R13 B A ... 3 2 Figure Q4. ww ww

c. Sketch the zero-pole plot and the direct form II diagram of the completed design out of part b. d. Calculate and sketch the output sequence after feeding x [n] into this system.

A 12-bit D/A converter has a full scale voltage of 10.00 V. What is the voltage corresponding to the LSB? To the MSB? What is the output voltage if the binary input code is equal to (100100100101)?

1. Suppose that you have a 12-bit, successive approximation register (SAR) A/D converter with a total conversion time of 100 microseconds (including sampling time). a). What is the maximum frequency of an analog signal that it can capture? b). Suppose that the converter can convert an input voltage over the range of 0 to +3.3V, what is the minimum voltage change that should be measurable by this converter? c). What is the quantization error of the ADC?

What is the maximum conversion time for a 16-bit dual-ramp converter using a 1-MHz clock frequency? What is the maximum conversion rate?